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Date: Sat, 24 Oct 2015 10:33:12 -0800
Message-ID: <CAC4O8c-5ukywtH+-=Zs=BXvLtn7WwdrabapkyrhEU7=ssvXqJA@mail.gmail.com>
Subject: Re: [geda-user] Star shorts
From: "Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On Fri, Oct 23, 2015 at 9:07 PM, Larry Doolittle <ldoolitt AT recycle DOT lbl DOT gov>
wrote:

> Britton -
>
> On Fri, Oct 23, 2015 at 08:10:27PM -0800, Britton Kerin (
> britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:
> > On Thu, Oct 22, 2015 at 9:02 AM, Larry Doolittle <
> ldoolitt AT recycle DOT lbl DOT gov>
> > wrote:
> > > On Thu, Oct 22, 2015 at 12:43:15PM -0400, DJ Delorie wrote:
> > > > One of our old problems is "how to tell where a short really is".
> > > > Perhaps that problem and "where is a star ground" are really the same
> > > > problem?  We'd just need some way of saying "we expect these nets to
> > > > be shorted".
> > > No, that's the wrong answer, since it's exactly the same as having
> > > one net.  We're looking for a way to say "we expect these nets to be
> > > shorted _in_exactly_one_place".  And an acceptable solution involves
> > > specifying where that place is.
> > Having been working on DRC lately I can confirm that this would be
> > extremely painful to implement.  I don't think its worth it, compared to
> > putting a symbol into the schematic to record the limited nature of the
> > connection as John suggests.  This approach avoids any new implementation
> > work and maintains as invariant the normal meaning of connectivity at the
> > interface level.
>
> There are multiple angles to this problem.
>  - the gschem end
>  - the rendition of this semantics in (one of many) netlist formats
>  - the treatment of that netlist information in board layout (or other
> hardware)
>
> At the gschem end, and the netlist representation, I don't see any
> sensible approach besides having a symbol and a component.  I'm pretty
> sure that's what you (Britton) are advocating, and if so we agree.
> Maybe there's some magic so that this symbol/component can have an
> arbitrary number of pins, or maybe we just punt and create hard-coded
> symbol/component sets with 2, 3, 4, 5 pins.
>

I would punt as you suggest here.  We aren't talking about a large family
of parts.


> On to PCB (or any other layout too; John Doty can close his ears for
> this part).  AFAICT, there is no established technique to implement
> such a star short in a way that will pass DRC.  There needs to be
> copper half-inside the DRC process, that definitely shows up on the
> Gerber output.  This copper can't exist during the netlist check
> (optimize rats).


> To my feeble brain (it's been a difficult week) it would make sense
> to use a special-purpose layer for this job.  The star short component
> would put copper on it.  it would show up as part of one layer
> for every step except the rats processor.  I guess this extra layer
> could be paired with any copper layer?  And you could have star
> grounds (and this layer) for any copper layer?  The footprint would
> have to be carefully designed (and maybe depend on the design rules?)
> so that there's no chance of any copper, other than the wires attaching
> to the star, touching the ghost copper that makes the short.
>

Another option would be to somehow have pcb keep it's nose out of any
connectivity that happens intra-footprint, since that's none of its
business, and make overlapping pads.  I was going to propose this, and then
realized that pcb would actually probably consider it a short.  So I think
 the current behavior (assuming it does complain) is not intuitive.  This
could lead to nasty results for broken footprints of course, but broken
(e.g. pin-swapped) footprints are always nasty and there's nothing gEDA can
do to catch that sort of thing.

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<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On Fri, Oct 23, 2015 at 9:07 PM, Larry Doolittle <span dir=3D"ltr">&lt;=
<a href=3D"mailto:ldoolitt AT recycle DOT lbl DOT gov" target=3D"_blank">ldoolitt AT recy=
cle.lbl.gov</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" styl=
e=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Britton=
 -<br>
<br>
On Fri, Oct 23, 2015 at 08:10:27PM -0800, Britton Kerin (<a href=3D"mailto:=
britton DOT kerin AT gmail DOT com">britton DOT kerin AT gmail DOT com</a>) [via <a href=3D"mailt=
o:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>] wrote:<br>
&gt; On Thu, Oct 22, 2015 at 9:02 AM, Larry Doolittle &lt;<a href=3D"mailto=
:ldoolitt AT recycle DOT lbl DOT gov">ldoolitt AT recycle DOT lbl DOT gov</a>&gt;<br>
&gt; wrote:<br>
&gt; &gt; On Thu, Oct 22, 2015 at 12:43:15PM -0400, DJ Delorie wrote:<br>
&gt; &gt; &gt; One of our old problems is &quot;how to tell where a short r=
eally is&quot;.<br>
&gt; &gt; &gt; Perhaps that problem and &quot;where is a star ground&quot; =
are really the same<br>
&gt; &gt; &gt; problem?=C2=A0 We&#39;d just need some way of saying &quot;w=
e expect these nets to<br>
&gt; &gt; &gt; be shorted&quot;.<br>
&gt; &gt; No, that&#39;s the wrong answer, since it&#39;s exactly the same =
as having<br>
&gt; &gt; one net.=C2=A0 We&#39;re looking for a way to say &quot;we expect=
 these nets to be<br>
&gt; &gt; shorted _in_exactly_one_place&quot;.=C2=A0 And an acceptable solu=
tion involves<br>
&gt; &gt; specifying where that place is.<br>
&gt; Having been working on DRC lately I can confirm that this would be<br>
&gt; extremely painful to implement.=C2=A0 I don&#39;t think its worth it, =
compared to<br>
&gt; putting a symbol into the schematic to record the limited nature of th=
e<br>
&gt; connection as John suggests.=C2=A0 This approach avoids any new implem=
entation<br>
&gt; work and maintains as invariant the normal meaning of connectivity at =
the<br>
&gt; interface level.<br>
<br>
There are multiple angles to this problem.<br>
=C2=A0- the gschem end<br>
=C2=A0- the rendition of this semantics in (one of many) netlist formats<br=
>
=C2=A0- the treatment of that netlist information in board layout (or other=
 hardware)<br>
<br>
At the gschem end, and the netlist representation, I don&#39;t see any<br>
sensible approach besides having a symbol and a component.=C2=A0 I&#39;m pr=
etty<br>
sure that&#39;s what you (Britton) are advocating, and if so we agree.<br>
Maybe there&#39;s some magic so that this symbol/component can have an<br>
arbitrary number of pins, or maybe we just punt and create hard-coded<br>
symbol/component sets with 2, 3, 4, 5 pins.<br></blockquote><div><br></div>=
<div style=3D"">I would punt as you suggest here.=C2=A0 We aren&#39;t talki=
ng about a large family of parts.</div><div>=C2=A0</div><blockquote class=
=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padd=
ing-left:1ex">
On to PCB (or any other layout too; John Doty can close his ears for<br>
this part).=C2=A0 AFAICT, there is no established technique to implement<br=
>
such a star short in a way that will pass DRC.=C2=A0 There needs to be<br>
copper half-inside the DRC process, that definitely shows up on the<br>
Gerber output.=C2=A0 This copper can&#39;t exist during the netlist check<b=
r>
(optimize rats).</blockquote><blockquote class=3D"gmail_quote" style=3D"mar=
gin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
To my feeble brain (it&#39;s been a difficult week) it would make sense<br>
to use a special-purpose layer for this job.=C2=A0 The star short component=
<br>
would put copper on it.=C2=A0 it would show up as part of one layer<br>
for every step except the rats processor.=C2=A0 I guess this extra layer<br=
>
could be paired with any copper layer?=C2=A0 And you could have star<br>
grounds (and this layer) for any copper layer?=C2=A0 The footprint would<br=
>
have to be carefully designed (and maybe depend on the design rules?)<br>
so that there&#39;s no chance of any copper, other than the wires attaching=
<br>
to the star, touching the ghost copper that makes the short.<br></blockquot=
e><div><br></div><div style=3D"">Another option would be to somehow have pc=
b keep it&#39;s nose out of any connectivity that happens intra-footprint, =
since that&#39;s none of its business, and make overlapping pads.=C2=A0 I w=
as going to propose this, and then realized that pcb would actually probabl=
y consider it a short.=C2=A0 So I think =C2=A0the current behavior (assumin=
g it does complain) is not intuitive.=C2=A0 This could lead to nasty result=
s for broken footprints of course, but broken (e.g. pin-swapped) footprints=
 are always nasty and there&#39;s nothing gEDA can do to catch that sort of=
 thing.</div><div><br></div></div></div></div>

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