On Fri, Oct 23, 2015 at 9:07 PM, Larry Doolittle <= ldoolitt AT recy= cle.lbl.gov> wrote:

Britton= -

On Fri, Oct 23, 2015 at 08:10:27PM -0800, Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:
> On Thu, Oct 22, 2015 at 9:02 AM, Larry Doolittle <ldoolitt AT recycle DOT lbl DOT gov>
> wrote:
> > On Thu, Oct 22, 2015 at 12:43:15PM -0400, DJ Delorie wrote:
> > > One of our old problems is "how to tell where a short r= eally is".
> > > Perhaps that problem and "where is a star ground" = are really the same
> > > problem?=C2=A0 We'd just need some way of saying "w= e expect these nets to
> > > be shorted".
> > No, that's the wrong answer, since it's exactly the same = as having
> > one net.=C2=A0 We're looking for a way to say "we expect= these nets to be
> > shorted _in_exactly_one_place".=C2=A0 And an acceptable solu= tion involves
> > specifying where that place is.
> Having been working on DRC lately I can confirm that this would be
> extremely painful to implement.=C2=A0 I don't think its worth it, = compared to
> putting a symbol into the schematic to record the limited nature of th= e
> connection as John suggests.=C2=A0 This approach avoids any new implem= entation
> work and maintains as invariant the normal meaning of connectivity at = the
> interface level.

There are multiple angles to this problem.
=C2=A0- the gschem end
=C2=A0- the rendition of this semantics in (one of many) netlist formats =C2=A0- the treatment of that netlist information in board layout (or other= hardware)

At the gschem end, and the netlist representation, I don't see any
sensible approach besides having a symbol and a component.=C2=A0 I'm pr= etty
sure that's what you (Britton) are advocating, and if so we agree.
Maybe there's some magic so that this symbol/component can have an
arbitrary number of pins, or maybe we just punt and create hard-coded
symbol/component sets with 2, 3, 4, 5 pins.

I would punt as you suggest here.=C2=A0 We aren't talki= ng about a large family of parts.

=C2=A0

On to PCB (or any other layout too; John Doty can close his ears for
this part).=C2=A0 AFAICT, there is no established technique to implement such a star short in a way that will pass DRC.=C2=A0 There needs to be
copper half-inside the DRC process, that definitely shows up on the
Gerber output.=C2=A0 This copper can't exist during the netlist check (optimize rats).

To my feeble brain (it's been a difficult week) it would make sense
to use a special-purpose layer for this job.=C2=A0 The star short component=
would put copper on it.=C2=A0 it would show up as part of one layer
for every step except the rats processor.=C2=A0 I guess this extra layer could be paired with any copper layer?=C2=A0 And you could have star
grounds (and this layer) for any copper layer?=C2=A0 The footprint would have to be carefully designed (and maybe depend on the design rules?)
so that there's no chance of any copper, other than the wires attaching=
to the star, touching the ghost copper that makes the short.

Another option would be to somehow have pc= b keep it's nose out of any connectivity that happens intra-footprint, = since that's none of its business, and make overlapping pads.=C2=A0 I w= as going to propose this, and then realized that pcb would actually probabl= y consider it a short.=C2=A0 So I think =C2=A0the current behavior (assumin= g it does complain) is not intuitive.=C2=A0 This could lead to nasty result= s for broken footprints of course, but broken (e.g. pin-swapped) footprints= are always nasty and there's nothing gEDA can do to catch that sort of= thing.