Mail Archives: djgpp/1999/01/25/08:25:32
Allens <allen DOT asjp AT cableol DOT co DOT uk> wrote:
> Unless I have missed something *big* a PII is just a combination of a P PRO
> (on-chip level 2 cache) and MMX,
That's true PII are CPUs with P6 core and MMX.
> so the only optimisations you can do are the
> mmx ones,
Wrong:
1) gcc (and I think any C compiler) can't optimize using MMX.
2) P6 core have some instructions *not* found in P5. One if a *very* good
instruction "Asign conditionally". Lamentably gcc have a bug and assigns when
doesn;t have to do it (the boolean value is reversed :-( ).
> and lots and lots of register variables to fill up that 512Kb level 2
> cache (Which AFAIK O2+ does for you). I'm not sure whether pgcc has any mmx
> specific code, I have a feeling it doesn't.
To exploit SIMD instructions (like MMX) you need to at least define some
macros to help the compiler. You can find a link in my links collection to a
modified version of gcc that can generate MMX optimized code, but using some
special macros! in fact the optimal thing is add some C operators to allow
the programmer define the parallelism in the code and hence enable the
compiler to process more than one value in parallel (that's what MMX is
supposed to do).
SET
------------------------------------ 0 --------------------------------
Visit my home page: http://welcome.to/SetSoft
or
http://www.geocities.com/SiliconValley/Vista/6552/
Salvador Eduardo Tropea (SET). (Electronics Engineer)
Alternative e-mail: set-soft AT usa DOT net set AT computer DOT org
ICQ: 2951574
Address: Curapaligue 2124, Caseros, 3 de Febrero
Buenos Aires, (1678), ARGENTINA
TE: +(541) 759 0013
- Raw text -