Message-Id: <m104lyk-000S2PC@inti.gov.ar>
Comments: Authenticated sender is <salvador AT natacha DOT inti DOT gov DOT ar>
From: "Salvador Eduardo Tropea (SET)" <salvador AT inti DOT gov DOT ar>
Organization: INTI
To: Allens <allen DOT asjp AT cableol DOT co DOT uk>, djgpp AT delorie DOT com
Date: Mon, 25 Jan 1999 10:28:50 +0000
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Subject: Re: Pentium II optimizations
In-reply-to: <36AA1508.95AFE993@cableol.co.uk>
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Reply-To: djgpp AT delorie DOT com

Allens <allen DOT asjp AT cableol DOT co DOT uk> wrote:

> Unless I have missed something *big* a PII is just a combination of a P PRO
> (on-chip level 2 cache) and MMX, 

That's true PII are CPUs with P6 core and MMX.

> so the only optimisations you can do are the
> mmx ones, 

Wrong:

1) gcc (and I think any C compiler) can't optimize using MMX.
2) P6 core have some instructions *not* found in P5. One if a *very* good 
instruction "Asign conditionally". Lamentably gcc have a bug and assigns when 
doesn;t have to do it (the boolean value is reversed :-( ).

> and lots and lots of register variables to fill up that 512Kb level 2
> cache (Which AFAIK O2+ does for you).  I'm not sure whether pgcc has any mmx
> specific code, I have a feeling it doesn't.

To exploit SIMD instructions (like MMX) you need to at least define some 
macros to help the compiler. You can find a link in my links collection to a 
modified version of gcc that can generate MMX optimized code, but using some 
special macros! in fact the optimal thing is add some C operators to allow 
the programmer define the parallelism in the code and hence enable the 
compiler to process more than one value in parallel (that's what MMX is 
supposed to do).

SET 
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