From patchwork Fri Jan 3 19:23:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: mirabilos X-Patchwork-Id: 104004 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 263423858C42 for ; Fri, 3 Jan 2025 19:25:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 263423858C42 X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from herc.mirbsd.org (herc.mirbsd.org [IPv6:2001:470:1f15:10c:202:b3ff:feb7:54e8]) by sourceware.org (Postfix) with ESMTPS id 097BC3858C5F for ; Fri, 3 Jan 2025 19:24:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 097BC3858C5F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=debian.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=debian.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 097BC3858C5F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:1f15:10c:202:b3ff:feb7:54e8 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735932279; cv=none; b=YzDdIrfh06fiSqx7xPDt2aFkIzIK3j0qZCAPanKwHqgmyHoEf0NvZ9W7v9oJbR+8wWOo+VXnxaL7f1jyE0PENkQo6+8iztiJ9a4et95203E6kE5X09V/ELac6gTHCLrtZGShpQAhgNJwoc1Z8dOWWWTF8EylYWKN4e/Q202hj6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1735932279; c=relaxed/simple; bh=nElS/O6EvggQ1+jP728FQSulUkD786UcMdT5Ed05Hvw=; h=Date:From:To:Subject:Message-ID:MIME-Version; b=FAYGNN8wFGWVkWsbqvxuT8bSl4fBO1J6WElK+9R+NE4Gw7UTOrtZ+AAewEMRndFOzSfylG8LueKehH1DFc3ZDMoli09qroZWo2fX6H2DXtvqc9RbRnW3V6tM0DJiBJ8OeTQvukER+3kvoZ7cbZm4LmjK+x86G8IF3NOMp2eT3rs= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 097BC3858C5F Received: from herc.mirbsd.org (tg@herc.mirbsd.org [192.168.0.82]) by herc.mirbsd.org (8.14.9/8.14.5) with ESMTP id 503JNvLj011936 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 3 Jan 2025 19:24:03 GMT Date: Fri, 3 Jan 2025 19:23:57 +0000 (UTC) From: mirabilos X-X-Sender: tg@herc.mirbsd.org To: libc-alpha@sourceware.org cc: Adhemerval Zanella Netto , John Paul Adrian Glaubitz Subject: [PATCH] sh4: ensure FPSCR.PR==0 when executing FRCHG [BZ #27543] Message-ID: Content-Language: de-Zsym-DE-1901-u-em-text-rg-denw-tz-utc, en-Zsym-GB-u-cu-eur-em-text-fw-mon-hc-h23-ms-metric-mu-celsius-rg-denw-tz-utc-va-posix MIME-Version: 1.0 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org If the bit is not 0, the operations FRCHG and FSCHG are undefined and cause a trap; qemu now checks for this as well, so we set it to 0 temporarily and restore the old value in getcontext afterwards (setcontext/swapcontext already do so). From the discussion in the bugreport, this can probably be optimised in one place but none of the people involved are SH4 assembly experts, this patch is field-tested, and it’s not a code path run often. The other question, what happens if a signal occurs while the bit is temporarily 0, is also still unsolved, but to fix that a kernel change is most likely needed; this patch changes a certain trap on many CPUs for a hard-to-get trap in a signal handler if a signal is delivered during the few instructions the PR bit is temporarily set to 0, so it’s not a regression for most users. See BZ and https://bugs.launchpad.net/qemu/+bug/1796520 for related discussion, references and review comments. Signed-off-by: mirabilos Reviewed-by: Oleg Endo Tested-by: John Paul Adrian Glaubitz --- sysdeps/unix/sysv/linux/sh/sh4/getcontext.S | 6 ++++++ sysdeps/unix/sysv/linux/sh/sh4/setcontext.S | 2 ++ sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S | 2 ++ 3 files changed, 10 insertions(+) From b9015c5a51bfbf3b7dc59f52620a8d5ca307c54b Mon Sep 17 00:00:00 2001 From: mirabilos Date: Fri, 3 Jan 2025 18:53:21 +0000 Subject: [PATCH] sh4: ensure FPSCR.PR==0 when executing FRCHG [BZ #27543] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: libc-alpha@sourceware.org Cc: Adhemerval Zanella Netto , John Paul Adrian Glaubitz If the bit is not 0, the operations FRCHG and FSCHG are undefined and cause a trap; qemu now checks for this as well, so we set it to 0 temporarily and restore the old value in getcontext afterwards (setcontext/swapcontext already do so). From the discussion in the bugreport, this can probably be optimised in one place but none of the people involved are SH4 assembly experts, this patch is field-tested, and it’s not a code path run often. The other question, what happens if a signal occurs while the bit is temporarily 0, is also still unsolved, but to fix that a kernel change is most likely needed; this patch changes a certain trap on many CPUs for a hard-to-get trap in a signal handler if a signal is delivered during the few instructions the PR bit is temporarily set to 0, so it’s not a regression for most users. See BZ and https://bugs.launchpad.net/qemu/+bug/1796520 for related discussion, references and review comments. Signed-off-by: mirabilos Reviewed-by: Oleg Endo Tested-by: John Paul Adrian Glaubitz --- sysdeps/unix/sysv/linux/sh/sh4/getcontext.S | 6 ++++++ sysdeps/unix/sysv/linux/sh/sh4/setcontext.S | 2 ++ sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S | 2 ++ 3 files changed, 10 insertions(+) -- 2.30.2 diff --git a/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S b/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S index 4470e5730b..329a790cd6 100644 --- a/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S @@ -67,6 +67,8 @@ ENTRY(__getcontext) add #(oFPUL+4-124),r0 sts.l fpul, @-r0 sts.l fpscr, @-r0 + mov #0, r6 + lds r6, fpscr frchg fmov.s fr15, @-r0 fmov.s fr14, @-r0 @@ -101,6 +103,10 @@ ENTRY(__getcontext) fmov.s fr2, @-r0 fmov.s fr1, @-r0 fmov.s fr0, @-r0 + mov r4, r0 + add #124, r0 + add #(oFPSCR-124), r0 + lds.l @r0+, fpscr #endif /* __SH_FPU_ANY__ */ /* sigprocmask (SIG_BLOCK, NULL, &uc->uc_sigmask). */ diff --git a/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S b/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S index a6d1de960c..60aff78256 100644 --- a/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S @@ -50,6 +50,8 @@ ENTRY(__setcontext) .Lsetcontext_restore: #ifdef __SH_FPU_ANY__ + mov #0, r9 + lds r9, fpscr mov r8, r0 add #(oFR0),r0 fmov.s @r0+, fr0 diff --git a/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S b/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S index a299e05b41..6cf88f2b68 100644 --- a/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S @@ -67,6 +67,8 @@ ENTRY(__swapcontext) add #(oFPUL+4-124),r0 sts.l fpul, @-r0 sts.l fpscr, @-r0 + mov #0, r9 + lds r9, fpscr frchg fmov.s fr15, @-r0 fmov.s fr14, @-r0