Hardware Interrupts

The programmable interrupt controllers are mapped by the DPMI host to the system's default interrupt assignments. On an IBM AT-compatible system, for example, the master interrupt controller (IRQ0 through IRQ7) is programmed to use a base interrupt level of 8 and the slave controller (IRQ8 through IRQ15) uses a base interrupt level of 70H.

All of the code and data that may be touched by hardware interrupt handlers must reside in locked memory to avoid page faults at interrupt time. The handler will always be called on a locked stack. As in real mode, hardware interrupt handlers are called with virtual interrupts disabled and the trace flag reset. In systems where the CPU's interrupt flag is virtualized, IRET may not restore the interrupt flag. Therefore, clients should execute a STI before executing IRET or else interrupts will remain disabled.

Protected mode hardware interrupt handlers that call a real mode routine must either ensure that the real mode code will not modify segment registers or user the DPMI state save/restore services (see page 94). However, any interrupt handler that executes completely in protected mode, or uses the translation services (Int 31H Functions 0300H, 0301H, or 0302H), does not need to save the real mode register state.

Personal computers with two programmable interrupt controllers usually have a BIOS that redirects one of the interrupts from the slave controller into the range of the master controller for compatibility with older, 8086/88-based systems. For example, devices jumpered for IRQ2 on PC/AT-compatible computers actually interrupt on IRQ 9 (Int 71H), but the BIOS on these systems converts Int 71H to Int 0AH yet sends the EOI command (appropriately) to the slave controller. A protected mode client that needs access to the redirected interrupt might use a variation on one of the following techniques:

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