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Date: Tue, 30 Jun 1998 00:44:20 +0200
From: Remi Guyomarch <rguyom AT mail DOT dotcom DOT fr>
Organization: Me ? Organized ?
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To: beastium <beastium-list AT Desk DOT nl>
Subject: Re: bzip2-mx vs. bzip2-nomx
References: <19980629155048 DOT 25657 AT cerebro DOT laendle>
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Sender: Marc Lehmann <pcg AT goof DOT com>
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Marc Lehmann wrote:

> it seems that, with improved scheduling and tuning, speed improvements are
> possible, at least on p-ii, where the slowdown is small. my tests indicate
> that the mmx unit on p-iis is suprisingly fast and can well execute a number
> of mmx instructions in parallel.
> 
> this doesn't seem to be the case on k6 or 6x86mx chips, which perform quite
> badly :( i believe mmx on these chips is useless for normal code and normal
> compilers that cannot take advantage of the parallelisation. I guess thats
> true for the pentium-mmx as well (though I have no data)

PII can dual-issue most MMX instructions (but since these instructions
are later converted to some other instruction set, it's not very clear).

Pentiums really have only one restriction : memory and integer register
access can only be made in the U pipe. This processor is amazing, it can
shift 64-bit entities faster than 32-bit ones : an MMX shift with the
count in a register cost only 1 clock where the same shift cost 4/5
clocks using 32-bit standard registers... Even better, the MMX shift can
be paired (with anything but another MMX shift or pack) and the standard
SHL reg,CL can't, mouarf !

The 6x86MX simply can't dual-issue MMX instructions, because it has only
one MMX core. Same thing for the K6.

K6-3D and K6-2 are much stronger in this area. They have a dual MMX core
and will perform better on MMX.

-- 
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