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Date: Fri, 23 Oct 2015 22:07:56 -0700
From: Larry Doolittle <ldoolitt AT recycle DOT lbl DOT gov>
To: "Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Subject: [geda-user] Star shorts
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Britton -

On Fri, Oct 23, 2015 at 08:10:27PM -0800, Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:
> On Thu, Oct 22, 2015 at 9:02 AM, Larry Doolittle <ldoolitt AT recycle DOT lbl DOT gov>
> wrote:
> > On Thu, Oct 22, 2015 at 12:43:15PM -0400, DJ Delorie wrote:
> > > One of our old problems is "how to tell where a short really is".
> > > Perhaps that problem and "where is a star ground" are really the same
> > > problem?  We'd just need some way of saying "we expect these nets to
> > > be shorted".
> > No, that's the wrong answer, since it's exactly the same as having
> > one net.  We're looking for a way to say "we expect these nets to be
> > shorted _in_exactly_one_place".  And an acceptable solution involves
> > specifying where that place is.
> Having been working on DRC lately I can confirm that this would be
> extremely painful to implement.  I don't think its worth it, compared to
> putting a symbol into the schematic to record the limited nature of the
> connection as John suggests.  This approach avoids any new implementation
> work and maintains as invariant the normal meaning of connectivity at the
> interface level.

There are multiple angles to this problem.
 - the gschem end
 - the rendition of this semantics in (one of many) netlist formats
 - the treatment of that netlist information in board layout (or other hardware)

At the gschem end, and the netlist representation, I don't see any
sensible approach besides having a symbol and a component.  I'm pretty
sure that's what you (Britton) are advocating, and if so we agree.
Maybe there's some magic so that this symbol/component can have an
arbitrary number of pins, or maybe we just punt and create hard-coded
symbol/component sets with 2, 3, 4, 5 pins.

On to PCB (or any other layout too; John Doty can close his ears for
this part).  AFAICT, there is no established technique to implement
such a star short in a way that will pass DRC.  There needs to be
copper half-inside the DRC process, that definitely shows up on the
Gerber output.  This copper can't exist during the netlist check
(optimize rats).

To my feeble brain (it's been a difficult week) it would make sense
to use a special-purpose layer for this job.  The star short component
would put copper on it.  it would show up as part of one layer
for every step except the rats processor.  I guess this extra layer
could be paired with any copper layer?  And you could have star
grounds (and this layer) for any copper layer?  The footprint would
have to be carefully designed (and maybe depend on the design rules?)
so that there's no chance of any copper, other than the wires attaching
to the star, touching the ghost copper that makes the short.

  - Larry