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Date: Thu, 22 Oct 2015 19:32:38 +0200 (CEST)
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Subject: Re: [geda-user] A lesson from gnet-makefile
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On Thu, 22 Oct 2015, Larry Doolittle wrote:

> DJ -
>
> On Thu, Oct 22, 2015 at 12:43:15PM -0400, DJ Delorie wrote:
>> One of our old problems is "how to tell where a short really is".
>> Perhaps that problem and "where is a star ground" are really the same
>> problem?  We'd just need some way of saying "we expect these nets to
>> be shorted".
>
> No, that's the wrong answer, since it's exactly the same as having
> one net.  We're looking for a way to say "we expect these nets to be
> shorted _in_exactly_one_place".  And an acceptable solution involves
> specifying where that place is.
>

I agree. In pcb-rnd I solve the "where the short is" problem using the 
minimal cut algorithm. It basically says "let's consider combination of 
cuts that would separate the shorted nets so that the problem is resolved; 
now let's find the solution(s) with the minimal number of cuts". A cut is 
a deletion of an object (e.g. a trace or a via).

While working on it, I enumerated cases in example inputs and found that 
there are often more than one solution to the problem. Even using 
different weights on edges, it's easy to construct symmetrical shorts 
that will yield two or more equally good solutions. For the star topology 
this means two equally good looking star points. Even if it is prepared to 
accept only one short, how the algorithm would decide which one is the 
good one?

I think Larry is right about PCB needs more information on the intention 
of the designer. I'd go one step further: it would be cool if we could 
pass generic DRC rules/considerations from the schematics to PCB, e.g. 
"the distance between this pin and that pin should be less than x" or if 
we somehow explain the star topology "the distance between the star point 
and this pin should be less than x".

Regards,

Igor2