X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; bh=agVc9nNSAgxcdkeGEGaGUroKyy6pP6lmqL4x5/N5G3g=; b=NW2PPd1SQuA87gCeKyTtonvaCweNrLAnVdQmTv6OAv9Tj0vxq8NaX9iI3d/pMMunVD TnKLVUCd1q9pbGfB1fBzXUpNSxbkfP733U+VILsImmPb76vVl4gohXzu+PdAiK6mZbp0 BgSOHFVx1XzZnpnoUsRNV2DeL61Rk3fdzyhXsWQXKmLCZLx2tzbMhdpzhTiWulTh/n5I 2rSpdIU8KPGsdF1/ekBubDnEdibs9r3Oxuz7fmyNB2wLa/SG44UXpTsKMtLSXenW9biz q/NUmyAXXT9CmGvc6TBSbi9h4zTiRfFLLpfm2v389blmhJba6gd2HDKa0TSvGpYGZNpr SApg== MIME-Version: 1.0 X-Received: by 10.112.64.72 with SMTP id m8mr4954842lbs.41.1444925500383; Thu, 15 Oct 2015 09:11:40 -0700 (PDT) In-Reply-To: <20151015122050.df4967802d7bf0e178ff2726@gmail.com> References: <20151015122050 DOT df4967802d7bf0e178ff2726 AT gmail DOT com> Date: Thu, 15 Oct 2015 12:11:40 -0400 Message-ID: Subject: Re: [geda-user] Design rule, suitable attributes at least for current From: "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" To: gEDA users mailing list Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by delorie.com id t9FGBjkR020356 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Thu, Oct 15, 2015 at 6:20 AM, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] wrote: > There have been discussions lately about attributes on pins and nets. On commercial tools I have used it is usually possible to specify minimum, standard and maximum value for width of traces. > > If current is specified instead of width it would be possible to use a mapping of currents to trace width which may be different for different layers and I actually think this approach would actually outperform the commercial tools. > > If current range which will be negative for opposite direction is specified for pins it would be possible for tools automatically calculate current range for all segments in circuit. Then maximum rms value have been calculated this could be used to automatically map currents to trace widths. You could write a backend to do that after we fix things so that nets are not flattened but some things need to be mentioned. While I like the idea in concept there are issues. For starters you would have to specify the copper thickness and if the trace was going to have solder mask removed and solder on it. Then there are the implications of ambient temperature the effect of which changes with airflow. When you get into some aspects of this it is possible to hit a higher level of complexity then you might expect from looking at the crude trace width calculators laying around the net most of which are really only good for DC (or fixed RMS AC), with no airflow, a stable ambient temperature and so on. This is why the other vendors let the user do the math. There are also times when trace thickness is not about current carrying capacity but other issues of signal integrity from parasitics, heat dissipation (ex LDO's using trace as heatsink), and etc. Meaning that you would want to be able to mix the two methods of specifying. I am not saying you should not pursue this, you are on the right track. I am just saying that there is more math involved and interdependencies with the rest of the layout that are not all apparent on the schematic. > Regards Nicklas Karlsson -- Home http://evanfoss.googlepages.com/ Work http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/