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From: "karl AT aspodata DOT se [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To: geda-user AT delorie DOT com
Subject: [geda-user] hierarchical pcb design
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Message-Id: <20221106075146.8A2B582601C2@turkos.aspodata.se>
Date: Sun,  6 Nov 2022 08:51:46 +0100 (CET)
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Reply-To: geda-user AT delorie DOT com

I have make:
 http://aspodata.se/git/openhw/bin/get_sub_pcbs.pl
as a prototype implementation for pcb sub design handling.

Using
 http://aspodata.se/git/openhw/boards_arm_aspo/stm32f100_styrkort/
as an example, doing:

$ get_sub_pcbs.pl power.sch

  gives me
$ ls -l *.pcb
-rw-r--r-- 1 karl users 43155 Nov  6 08:34 3pwr.mcp16301_3V3_sot666.pcb
-rw-r--r-- 1 karl users 43536 Nov  6 08:34 5pwr.mcp16301_5V_sot666_smd.pcb

  where:
$ diff 3pwr.mcp16301_3V3_sot666.pcb ../../share/gschem/_sub_page/pwr.mcp16301_3V3_sot666.pcb  | head -4
790c790
< Element["" "ipc7351b_3225Ar.fp" "3C3" "10u" 15.7000mm 3.4500mm 0.8000mm 1.8000mm 0 100 ""]
---
> Element["" "ipc7351b_3225Ar.fp" "C3" "10u" 15.7000mm 3.4500mm 0.8000mm 1.8000mm 0 100 ""]

Thoose two pcbs can then be loaded with
"Load layout data to paste-buffer" into your pcb design
and by that hierarchical pcb design is possible.

///

Anyone is welcome to implement this or something similar in
your favourite programming language, guile for lepton,
python for gschem, or c for pcb.

Regards,
/Karl Hammar