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Subject: Re: [geda-user] Power and IO symbols
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References: <alpine DOT DEB DOT 2 DOT 21 DOT 2012090007290 DOT 1129 AT nimbus>
 <20201209065927 DOT 985928512091 AT turkos DOT aspodata DOT se>
 <alpine DOT DEB DOT 2 DOT 21 DOT 2012091414150 DOT 1205 AT nimbus>
From: "Nicklas SB Karlsson (nk AT nksb DOT online) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Date: Fri, 5 Feb 2021 20:47:36 +0100
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Den 2020-12-09 kl. 14:33, skrev Roland Lutz:
> On Wed, 9 Dec 2020, karl AT aspodata DOT se [via geda-user AT delorie DOT com] wrote:
>> The netif_*.sym ones are useful in a subschematic. The vertical line 
>> marks the border/end/interface of a subschematc. Also I like the 
>> thicker line for power sym.
>
> Looking at these symbols, I see what you mean: your port symbols are 
> at the same time net symbols, so for example, an input called "in1" is 
> connected to the net called "in1" in the subschematic.
>
> Seeing how net and port symbols are now identical except for the 
> netname= / portname= attribute, I wonder if it may be a good idea to 
> remove this distinction and connect the pin of an instantiating 
> component not to a *component*, but to a *net* in the subschematic.
>
> Up until now, when a subschematic component is hooked up to the 
> subschematic(s) it instantiated, a pin with pinlabel=in1 on that 
> component is connected to a component with portname=in1 (or 
> refdes=in1) inside the subschematic.  This would change so it is 
> connected to the net named `in1' inside the subschematic.
>
> Pro: The confusion between netname= and portname= is resolved by 
> actually making it the same thing.

No do not think so then sub schematic is instantiated more than once, or?


Nicklas Karlsson