X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=optonline.net; s=dkim-001; t=1603646044; bh=dVI/dCZILd+cjoLUIoas3eex3bq+Y8POqnnrI76BNoM=; h=From:Date:Message-ID:Subject:To; b=gMhLNOPwX0QFPlWxcTQtnq7DOqMfHd1g+uLGs6h7Vht9gaUWH2Lyqo9QWMoCjLnN6 O3jDlei04pLkM7J4tSCp3omcZ5fcOhSFmL0y+SQajId+bgFMfRM3r76F/UaXdIB0Vu b05K4qMQF/51xr8t21QB0o+mokXEkgkPMbJOPkRwU2bwuMdJBx/9M9ZXLonyQEGp8v LW9Oc2Z7Z6vsN8fM6RpnSAtH8WWdsEta1bbU3+hbrxyA97nu5o7+lsK1dp/pMLj8GK u1OVNW3HXn67xq7NbpuS/vWIS5wU7Rx8vOthqi9cSY5gCLcJ6jGaDEetENAtCJJ+wq cxuGhOUVCJOCA== Authentication-Results: mta1.srv.hcvlny.cv.net x-tls.subject="/C=US/ST=California/L=Mountain View/O=Google LLC/CN=smtp.gmail.com"; auth=pass (cipher=AES128-GCM-SHA256) Authentication-Results: mta1.srv.hcvlny.cv.net smtp.user=geneglick; auth=pass (LOGIN) X-Content-Analysis: v=2.3 cv=OIq8IRSB c=1 sm=1 tr=0 a=0WrWrDzmOGG0pDJVai42kw==:117 a=afefHYAZSVUA:10 a=pGLkceISAAAA:8 a=Mj1Xp5F7AAAA:8 a=xRfjoxBpAAAA:8 a=GKgeRAecgC3ypEvw3QMA:9 a=xCif1Mbk0eSwVm3H:21 a=rMfZo4BrFHx-mHFH:21 a=QEXdDO2ut3YA:10 a=V1hWkF4OOrE1YlyFnDMA:9 a=JLO5rFVWMVnY7Zkg:21 a=7lzlm6Er0l4CyT-S:21 a=yIIMNuSSHQ9WqZ58:21 a=OCttjWrK5_uSHO_3Hkg-:22 a=4plUlNce3Gdv3FjnGo9M:22 X-Gm-Message-State: AOAM530kJjX/wfb9i1r+enu1HsQD37ZV/Bg65NsY7XkEoBRKKDQSeLR9 eaqafcZkVqiezmnoq6XWuYDuP+w5GwVqT+zRs5M= X-Google-Smtp-Source: ABdhPJwc70wgwRRxrVijX7uP6x/KQEp9E3XHftSYwiJdM0BkK75S1AyWCRIsu6CxB3jImCE1Scnh3V/EdNkBsICH1HE= X-Received: by 2002:a25:6e82:: with SMTP id j124mr14253055ybc.421.1603646038739; Sun, 25 Oct 2020 10:13:58 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: "gene glick (geneglick AT optonline DOT net) [via geda-user AT delorie DOT com]" Date: Sun, 25 Oct 2020 13:13:47 -0400 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [geda-user] PCB, 2 parts physically in the same place To: geda-user AT delorie DOT com Content-Type: multipart/alternative; boundary="0000000000007c124a05b281f0d0" Reply-To: geda-user AT delorie DOT com --0000000000007c124a05b281f0d0 Content-Type: text/plain; charset="UTF-8" Hi Chad, I'll send you the layout later today. It's non proprietary, just a personal project. The layout is complete, and I just have deleted the part from the layout, but not the schematic. So the program complains a little. I'll send you 2 versions. First the completed layout. Second, I'll add back the missing connector, remove the thermals and you can see for yourself. While writing this, it occurs to me that maybe I can add the thermals first and then place the 2nd connector in that same location. Gene On Sun, Oct 25, 2020, 11:26 AM Chad Parker (parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com] wrote: > Hi Gene- > > pcb will "allow" you to do basically anything. It should not prevent you > from overlapping the components. This shouldn't even generate a DRC warning. > > As a general rule, pcb assumes that the human designer knows best and > shouldn't prevent you from doing most things. It may complain with a DRC > warning, but it won't actually prevent you from doing it. > > Regarding the plane connection, pcb thermals should work for through-hole > components. The surface-mount thermals are implemented yet. > > I assume that the overlap warning isn't the one at 0,0 that we discussed > previously? It's helpful to have the problematic file to evaluate. I've > just done a couple of quick tests, and I am able to do what you're > describing in my test cases. > > Thanks, > --Chad > > On Sat, Oct 24, 2020 at 9:41 PM gene glick (geneglick AT optonline DOT net) [via > geda-user AT delorie DOT com] wrote: > >> I want to do this on purpose. One part, a 2X16 character display has 10 >> connections to the PCB. Problem is, they are just holes. It is meant to >> have a 10 pin header on the PCB, and then the display gets positioned over >> the header and soldered in place. So I placed a 10-pin header in the same >> location that the display holes. They line up perfectly but the sizes are >> slightly different (a little more or less annulus for example). >> >> I could simply get rid of the 10-pin header (yeah, I think that's the way >> to go in the short term), and remember to order it. If it's in the >> schematic though, it gets into the BOM...which is good. >> >> Anyway, PCB doesn't allow a couple of things - I cannot make a thermal >> connection to the plane on either top or bottom of board. Instead, I made >> some traces to the plane. Now DRC reports a problem with too little overlap. >> >> Is this a bug? >> > --0000000000007c124a05b281f0d0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Chad,

I&#= 39;ll send you the layout later today. It's non proprietary,=C2=A0 just= a personal project.=C2=A0 The layout is complete,=C2=A0 and I just have de= leted the part from the layout, but not the schematic. So the program compl= ains a little.=C2=A0

I&#= 39;ll send you 2 versions. First the completed layout.=C2=A0 Second,=C2=A0 = I'll add back the missing connector, remove the thermals and you can se= e for yourself.

While wr= iting this,=C2=A0 it occurs to me that maybe I can add the thermals first a= nd then place the 2nd connector in that same location.

Gene



Regarding the plane connection, pcb thermals should work for th= rough-hole components. The surface-mount thermals are implemented yet.

I assume that the overlap warning isn't the one at= 0,0 that we discussed previously? It's helpful to have the problematic= file to evaluate. I've just done a couple of quick tests, and I am abl= e to do what you're describing in my test cases.

Thanks,
--Chad

I want to do this on= purpose. One part, a 2X16 character display has 10 connections to the PCB.= Problem is, they are just holes. It is meant to have a 10 pin header on th= e PCB, and then the display gets positioned over the header and soldered in= place. So I placed a 10-pin header in the same location that the display h= oles. They line up perfectly but the sizes are slightly different (a little= more or less annulus for example).

I could simply= get rid of the 10-pin header (yeah, I think that's the way to go in th= e short term), and remember to order it. If it's in the schematic thoug= h, it gets into the BOM...which is good.

Anyway, P= CB doesn't allow a couple of things - I cannot make a thermal connectio= n to the plane on either top or bottom of board. Instead, I made some trace= s to the plane. Now DRC reports a problem with too little overlap.

Is this a bug?=C2=A0
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