X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-TCPREMOTEIP: 100.0.183.69 X-Authenticated-UID: jpd AT noqsi DOT com From: John Doty Content-Type: multipart/alternative; boundary="Apple-Mail=_F618F049-84FA-449B-AE11-AF9A3C28F2FE" Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.4\)) Subject: Re: [geda-user] A proposal to allow simulation only component to be embedded in schematics Date: Fri, 16 Oct 2020 19:06:08 -0400 References: <8e4ea0e5-a35f-59e3-8052-8e5901225461 AT epilitimus DOT com> <19E1ADF6-6DB0-44F2-B1BA-4FB0F34CF7E8 AT noqsi DOT com> <60f1ec51-d94b-e981-765b-a63b4012563c AT epilitimus DOT com> <9c3c750e-9c50-c12f-8660-ca9ca57b2a55 AT nksb DOT online> To: "Glenn (glimrick AT epilitimus DOT com) [via geda-user AT delorie DOT com]" In-Reply-To: <9c3c750e-9c50-c12f-8660-ca9ca57b2a55@nksb.online> Message-Id: <4F73D950-0204-441B-9B01-3F0739DA4869@noqsi.com> X-Mailer: Apple Mail (2.3608.120.23.2.4) Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --Apple-Mail=_F618F049-84FA-449B-AE11-AF9A3C28F2FE Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Oct 16, 2020, at 5:43 PM, Nicklas SB Karlsson (nk AT nksb DOT online) [via = geda-user AT delorie DOT com] wrote: >=20 > Use hierarchical design there one top level is used in ordinary = schematic while the other top level is used for simulation? That=E2=80=99s one way to do it. There are others. For a flat design, you can have a simulation page that injects power and = signals into named nets in the pages representing the board design. Just = leave that page out when building your layout netlist. Another way is to give the connectors on your board spice-prototype = attributes representing power and signal sources. The spice-noqsi back end is basically a macro expander for injecting = attributes into SPICE cards. How that works in your flow depends on how = you write your prototypes. The default prototypes mimic the spece-sdb = back end, but you need not go that way. John Doty Noqsi Aerospace, Ltd. jpd AT noqsi DOT com --Apple-Mail=_F618F049-84FA-449B-AE11-AF9A3C28F2FE Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8

On Oct 16, 2020, at 5:43 PM, Nicklas SB Karlsson (nk AT nksb DOT online) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

Use hierarchical design there = one top level is used in ordinary schematic while the other top level is = used for simulation?

That=E2=80=99s one way to do it. There are = others.

For a flat design, you can = have a simulation page that injects power and signals into named nets in = the pages representing the board design. Just leave that page out when = building your layout netlist.

Another = way is to give the connectors on your board spice-prototype attributes = representing power and signal sources.

The spice-noqsi back end is basically a macro = expander for injecting attributes into SPICE cards. How that works in = your flow depends on how you write your prototypes. The default = prototypes mimic the spece-sdb back end, but you need not go that = way.

John Doty = Noqsi = Aerospace, Ltd.

jpd AT noqsi DOT com

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