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        Mon, 20 May 2019 13:25:43 -0700 (PDT)
Date: Mon, 20 May 2019 23:25:41 +0300
From: "Vladimir Zhbanov (vzhbanov AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] Hierarchical Design for Spice
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Precedence: bulk

Hagen,

On Mon, May 20, 2019 at 09:45:05PM +0200, Hagen SANKOWSKI wrote:
> 
> Hello.
> 
> I draw one schematic for a circuit and an other schematic with the test
> bench stuff, instantiating the .SUBCKT.
> Well, I did not get it through the netlister export for spice..
> 
> I already google solutions and tried to figure out, what's going wrong.
> All ports are shorted with "rename shorted nets (net= has priority):"
> 
> Is there a How-To or Wiki which describes the process for Lepton-EDA or gEDA
> which works?

Please look at this nice resource by John Doty:

https://github.com/noqsi/gnet-spice-noqsi/wiki

The "spice-noqsi" backend should work with both gEDA and Lepton.
There is also a link to the howto by Stuart Brorson there.

HTH

-- 
  Vladimir

(λ)επτόν EDA — https://github.com/lepton-eda