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X-Envelope-From: hsank AT nospam DOT chipforge DOT org
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Date: Mon, 20 May 2019 21:45:05 +0200
Message-ID: <20190520214505.Horde.0UTCvzi8U9NvFR4qkIDRhiq@webmail.in-berlin.de>
From: Hagen SANKOWSKI <hsank AT nospam DOT chipforge DOT org>
To: geda-user AT delorie DOT com
Subject: [geda-user] Hierarchical Design for Spice
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Hello.

I draw one schematic for a circuit and an other schematic with the  
test bench stuff, instantiating the .SUBCKT.
Well, I did not get it through the netlister export for spice..

I already google solutions and tried to figure out, what's going wrong.
All ports are shorted with "rename shorted nets (net= has priority):"

Is there a How-To or Wiki which describes the process for Lepton-EDA  
or gEDA which works?

Best Regards,
Hagen.

-- 
"They who can give up essential liberty to obtain a little temporary
safety, deserve neither liberty nor safety." Benjamin Franklin (1775)