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References: <alpine DOT DEB DOT 2 DOT 00 DOT 1812140530380 DOT 21900 AT igor2priv>
 <CAKakQcfwxCititS-gcKyAuuawZoA1men4-O5vQ85eK8Y3OKk_g AT mail DOT gmail DOT com> <alpine DOT DEB DOT 2 DOT 00 DOT 1812151432380 DOT 21900 AT igor2priv>
In-Reply-To: <alpine.DEB.2.00.1812151432380.21900@igor2priv>
From: Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au>
Date: Mon, 17 Dec 2018 13:18:45 +1100
Message-ID: <CAKakQcddj77zaBOSsseFFzNOn_U7+d9SZQ+Zd-pTbuTS3UVHwg@mail.gmail.com>
Subject: Re: [geda-user] pcb: save connection data of - anyone ever used this?
To: geda-user AT delorie DOT com
Content-Type: text/plain; charset="UTF-8"
Reply-To: geda-user AT delorie DOT com

On Sun, Dec 16, 2018 at 12:43 AM <gedau AT igor2 DOT repo DOT hu> wrote:
> Since those times, we have introduced back annotation  [...]
> Would that make a good alternative to this custom export format?

Yes, back annotation would suit my needs well.

For me the best solution would be to support underconstrained
netlists; by this I mean a netlist where I can specify 8 data pins on
a DRAM IC and specify that each of those pins needs to connect to one
and only one of a set of (say) 10 pins on the FPGA.  During manual
routing selecting one of the DRAM data pins would highlight the 10
possible corresponding pins on the FPGA.
I'd love to have this feature, but not enough to invest the time to
code it up, so perhaps log it as a feature request for now :)

Best regards,
Stephen