X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Content-Type: multipart/alternative; boundary="2DKRVTMQSMTFXVUJYGXQRnhgwp" MIME-Version: 1.0 User-Agent: GWP-Draft X-Originator: 78.11.203.93 X-FactoryStamp: H--- Date: Tue, 15 May 2018 15:22:00 +0200 X-Draft-Variant: reply X-Draft-Parentmailid: 1d9ccea86c1fefb9fb1d7bac X-Draft-Contenttype: text/html Subject: =?UTF-8?Q?Re=3A_Odp=3A_Re=3A_=5Bgeda-user=5D_Opengl_PCB_and_mainline_PCB_-_pcb-rnd_aspects?= From: "michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delorie DOT com]" To: =?UTF-8?Q?geda-user=40delorie=2Ecom?= Message-ID: In-Reply-To: <> References: <647dca2ad89a4415ad980da6e5cdc701 AT grupawp DOT pl> <7da892c189bd49838d6ce6eb2c2628e4 AT grupawp DOT pl> <7e30777e38284644814271a68f2c2119 AT grupawp DOT pl> <00430c5cbe794d57918e5e9c532d436f AT grupawp DOT pl> X-WP-MailID: 492f0994234da360a1bc3cd114914319 X-WP-AV: skaner antywirusowy Poczty o2 X-WP-SPAM: NO 0000010 [gUMU] Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk --2DKRVTMQSMTFXVUJYGXQRnhgwp Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hello Igor, Have You received any mail from me recently? I'm not sure= what about the missing test You mentioned last time. Best Regards, Micha= el Widlok Dnia 11 maja 2018 09:35 michalwd1979 <gedau AT igor2 DOT repo= .hu> napisa=C5=82(a): Hello Michael, On Tue, 8 May 2018, michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delor= ie.com] wrote: RU200 is really the un-even Wilkinson splitter. The layout of it was given= to me in a dxf format, so I had to create a scaled background image and=C2= =A0 then draw polygons on it. Then the polygons were converted to a footprint = or Btw, we have a hpgl import plugin. Most CADs that can save in dxf can also= plot in hpgl. We don't yet deal with polygons, but it'd be easy to= add and then no redraw needed for such cases. <snip> As for vias that was a bit boring but not to much... The vias are the last= thing placed on the pcb so I had a nice felling of work-ending-soon when placing them :-). I thing that via-lines would be really useful only if the vias would be configurable in some way: connect using thermal X to polygon Y, with clearance Z or something. For example You create a via with all the specification needed and then "extend" it to a via-line. Was that = Yours idea? If yes then I would really like it. Yes. In pcb-rnd terminology your via is really a padstack, and a padstack = has a prototype (that describes the geometry). So for a via-line, you'= d select a padstack prototype and all vias on that line would be using that.= Just like multiple vias can share the same prototype today, multiple via-lines could share the same prototype. This means if you change the geomerty of the prototype, that immediately affects all instances. Another extra parameter for the via-line would be the spacing between vias= and how to enforce it (e.g. make sure endpoints have vias and tune the spacing to meet that, or rather keep the spacing as specified and don'= t mind if the second endpoint won't have a via). I also plan to have via-polygons - same story as via-lines: an evenly spaced grid of vias over an area specified by a virtual polygon. Would be = useful for those via grids under center pads of QFNs. Btw, any news on the dash-freq test on your system? We really need to know= the result to be able to go on with narrowing down what's causes the rendering slowness there. Regards, Igor2=0D --2DKRVTMQSMTFXVUJYGXQRnhgwp Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=UTF-8
Hello Igor,

Have You receiv= ed any mail from me recently? I'm not sure what about the missing test You = mentioned last time.
Best Regards,
Michael Widl= ok

Dnia 11 maja 2018 09:35 michalwd1979 <gedau AT igor2 DOT repo= .hu> napisa=C5=82(a):

Hello Michael,

On Tue, 8 May 2018, michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT d= elorie.com] wrote:

RU200 is really the un-even Wilkinson splitter. The layout of it was g= iven
to me in a dxf format, so I had to create a scaled background image an= d=C2=A0
then draw polygons on it. Then the polygons were converted to a footpr= int or

Btw, we have a hpgl import plugin. Most CADs that can save in dxf can = also
plot in hpgl. We don't yet deal with polygons, but it'd be eas= y to add and
then no redraw needed for such cases.

<snip>

As for vias that was a bit boring but not to much... The vias are the = last
thing placed on the pcb so I had a nice felling of work-ending-soon wh= en
placing them :-).
I thing that via-lines would be really useful only if the vias would b= e
configurable in some way: connect using thermal X to polygon Y, with
clearance Z or something. For example You create a via with all the
specification needed and then "extend" it to a via-line. Was t= hat Yours
idea? If yes then I would really like it.

Yes. In pcb-rnd terminology your via is really a padstack, and a padst= ack
has a prototype (that describes the geometry). So for a via-line, you&= #39;d
select a padstack prototype and all vias on that line would be using t= hat.

Just like multiple vias can share the same prototype today, multiple <= /div>
via-lines could share the same prototype. This means if you change the=
geomerty of the prototype, that immediately affects all instances.

Another extra parameter for the via-line would be the spacing between = vias
and how to enforce it (e.g. make sure endpoints have vias and tune the=
spacing to meet that, or rather keep the spacing as specified and don&= #39;t
mind if the second endpoint won't have a via).

I also plan to have via-polygons - same story as via-lines: an evenly =
spaced grid of vias over an area specified by a virtual polygon. Would= be
useful for those via grids under center pads of QFNs.



Btw, any news on the dash-freq test on your system? We really need to = know
the result to be able to go on with narrowing down what's causes t= he
rendering slowness there.

Regards,

Igor2
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