X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Fri, 11 May 2018 09:21:21 +0200 (CEST) X-X-Sender: igor2 AT igor2priv To: "michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delorie DOT com]" X-Debug: to=geda-user AT delorie DOT com from="gedau AT igor2 DOT repo DOT hu" From: gedau AT igor2 DOT repo DOT hu Subject: Re: Odp: Re: [geda-user] Opengl PCB and mainline PCB - pcb-rnd aspects In-Reply-To: <00430c5cbe794d57918e5e9c532d436f@grupawp.pl> Message-ID: References: <647dca2ad89a4415ad980da6e5cdc701 AT grupawp DOT pl> <7da892c189bd49838d6ce6eb2c2628e4 AT grupawp DOT pl> <7e30777e38284644814271a68f2c2119 AT grupawp DOT pl> <00430c5cbe794d57918e5e9c532d436f AT grupawp DOT pl> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="0-1044623009-1526023281=:8169" Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --0-1044623009-1526023281=:8169 Content-Type: TEXT/PLAIN; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Hello Michael, On Tue, 8 May 2018, michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delori= e.com] wrote: >RU200 is really the un-even Wilkinson splitter. The layout of it was given >to me in a dxf format, so I had to create a scaled background image and=C2= =A0 >then draw polygons on it. Then the polygons were converted to a footprint = or Btw, we have a hpgl import plugin. Most CADs that can save in dxf can also= =20 plot in hpgl. We don't yet deal with polygons, but it'd be easy to add and= =20 then no redraw needed for such cases. >As for vias that was a bit boring but not to much... The vias are the last >thing placed on the pcb so I had a nice felling of work-ending-soon when >placing them :-). >I thing that via-lines would be really useful only if the vias would be >configurable in some way: connect using thermal X to polygon Y, with >clearance Z or something. For example You create a via with all the >specification needed and then "extend" it to a via-line. Was that Yours >idea? If yes then I would really like it. Yes. In pcb-rnd terminology your via is really a padstack, and a padstack= =20 has a prototype (that describes the geometry). So for a via-line, you'd=20 select a padstack prototype and all vias on that line would be using that. Just like multiple vias can share the same prototype today, multiple=20 via-lines could share the same prototype. This means if you change the=20 geomerty of the prototype, that immediately affects all instances. Another extra parameter for the via-line would be the spacing between vias= =20 and how to enforce it (e.g. make sure endpoints have vias and tune the=20 spacing to meet that, or rather keep the spacing as specified and don't=20 mind if the second endpoint won't have a via). I also plan to have via-polygons - same story as via-lines: an evenly=20 spaced grid of vias over an area specified by a virtual polygon. Would be= =20 useful for those via grids under center pads of QFNs. Btw, any news on the dash-freq test on your system? We really need to know= =20 the result to be able to go on with narrowing down what's causes the=20 rendering slowness there. Regards, Igor2 --0-1044623009-1526023281=:8169--