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Date: Sun, 13 Aug 2017 16:05:19 +0200
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Subject: Re: [geda-user] pcb slotted holes for relay
To: geda-user AT delorie DOT com, gedau AT igor2 DOT repo DOT hu
From: "Carlos Nieves (cnieves DOT mail AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Hi,
I think both options can be needed=2E The usual way would be option B=2E

Option A can be used for other complex things=2E=2E=2E

I remember seeing some special PCB supplier supports components inside a c=
avity=2E I mean being able to place a smd component to be soldered at layer=
 3, for example, in a PCB with more than 4 layers=2E There is a hole or cav=
ity in layers 1 and 2 to allow this=2E

Of course this is not usual=2E=2E=2E But please design the core properly s=
o everything could be done at some point in the future=2E=2E=2E

Regards,

Carlos

El 13 de agosto de 2017 14:53:57 CEST, gedau AT igor2=2Erepo=2Ehu escribi=C3=
=B3:
>
>
>On Sun, 13 Aug 2017, Carlos Nieves wrote:
>
>> I don't think this is the right way=2E=2E=2E Specially for plated holes=
=2E
>Fabs usually check that there is a distance between copper and the
>board outline, so copper is not exposed at edges=2E
>> Doing it that way will results in failing that drc and having to
>postprocess the outline file=2E=2E=2E
>
>Well, the complete final solution would one of these:
>
>Option A:
>
>1=2E you define two layers groups, both with type "outline" so that
>pcb-rnd=20
>understands they are milled with a router; one of them is the real
>outline=20
>layer and unplated slots, the other is the plated slots [this is not
>yet=20
>possible, pcb-rnd assumes there's only one outline layer; not terribly=20
>hard to fix]
>
>2=2E the slot layer needs to be marked as 'plated' so all objects=20
>drawn there behave like vias, connecting layers [not yet possible;=20
>somewhat harder to do, but still on the relatively easy side]
>
>3=2E implement your footprint as a subcircuit, draw your slot as a line
>on=20
>the 'slot' layer; this will result in a plated slot; you may want to
>add=20
>some copper lines/polys around it on the top and bottom sides [this is=20
>already possible since release 1=2E2=2E4]
>
>4=2E tag the slot and the top/bottom copper lines/polys to the same
>terminal=20
>("pin number") so the netlist understands the connection [I'm working
>on=20
>this these days, will be possible in 1=2E=2E2 weeks]
>
>5=2E on export you simply get a normal unplated outline layer and a
>plated=20
>slot layer separately; you can then name the files accordingly or tell
>the=20
>fab house and I am sure they will understand not to run the=20
>copper-distance DRC on the slots [this step, exporting multiple outline
>
>layers, is already possible, if an export naming style is selected that
>
>doesn't result in overwriting the same file twice]
>
>Option B:
>
>after the subcircuit upgrade, next target will be pad stacks=2E I am
>tempted=20
>to introduce "hole shapes": for a common via or pin you'd use a
>circular=20
>hole (drill) but it would also allow lines for slots=2E This way the=20
>resulting construct is like a via (pin) in all regards=2E According to my
>
>current plans I will probably start coding pad stacks this year; having
>
>non-circular hole is a smallish task compared to the rest pad stacks
>need,=20
>so it's rather probable that we have this=2E In this setup the slots
>would=20
>end up in the plated drill file, much like your example showed=2E
>
>
>
>Note: eventually both methods will be available=2E The only question is=
=20
>when, which also depends on how much pull they get from active pcb-rnd=20
>users=2E At the moment pad stack seems to be the one that would be=20
>implemented first=2E
>
>Regards,
>
>Igor2

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<html><head></head><body>Hi,<br>
I think both options can be needed=2E The usual way would be option B=2E<b=
r>
<br>
Option A can be used for other complex things=2E=2E=2E<br>
<br>
I remember seeing some special PCB supplier supports components inside a c=
avity=2E I mean being able to place a smd component to be soldered at layer=
 3, for example, in a PCB with more than 4 layers=2E There is a hole or cav=
ity in layers 1 and 2 to allow this=2E<br>
<br>
Of course this is not usual=2E=2E=2E But please design the core properly s=
o everything could be done at some point in the future=2E=2E=2E<br>
<br>
Regards,<br>
<br>
Carlos<br><br><div class=3D"gmail_quote">El 13 de agosto de 2017 14:53:57 =
CEST, gedau AT igor2=2Erepo=2Ehu escribi=C3=B3:<blockquote class=3D"gmail_quot=
e" style=3D"margin: 0pt 0pt 0pt 0=2E8ex; border-left: 1px solid rgb(204, 20=
4, 204); padding-left: 1ex;">
<pre class=3D"k9mail"><br /><br />On Sun, 13 Aug 2017, Carlos Nieves wrote=
:<br /><br /><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 1ex=
 0=2E8ex; border-left: 1px solid #729fcf; padding-left: 1ex;"> I don't thin=
k this is the right way=2E=2E=2E Specially for plated holes=2E Fabs usually=
 check that there is a distance between copper and the board outline, so co=
pper is not exposed at edges=2E<br /> Doing it that way will results in fai=
ling that drc and having to postprocess the outline file=2E=2E=2E<br /></bl=
ockquote><br />Well, the complete final solution would one of these:<br /><=
br />Option A:<br /><br />1=2E you define two layers groups, both with type=
 &quot;outline&quot; so that pcb-rnd <br />understands they are milled with=
 a router; one of them is the real outline <br />layer and unplated slots, =
the other is the plated slots [this is not yet <br />possible, pcb-rnd assu=
mes there's only one outline layer; not terribly <br />hard to fix]<br /><b=
r />2=2E the slot layer needs to be marked as 'plated' so all objects <br /=
>drawn there behave like vias, connecting layers [not yet possible; <br />s=
omewhat harder to do, but still on the relatively easy side]<br /><br />3=
=2E implement your footprint as a subcircuit, draw your slot as a line on <=
br />the 'slot' layer; this will result in a plated slot; you may want to a=
dd <br />some copper lines/polys around it on the top and bottom sides [thi=
s is <br />already possible since release 1=2E2=2E4]<br /><br />4=2E tag th=
e slot and the top/bottom copper lines/polys to the same terminal <br />(&q=
uot;pin number&quot;) so the netlist understands the connection [I'm workin=
g on <br />this these days, will be possible in 1=2E=2E2 weeks]<br /><br />=
5=2E on export you simply get a normal unplated outline layer and a plated =
<br />slot layer separately; you can then name the files accordingly or tel=
l the <br />fab house and I am sure they will understand not to run the <br=
 />copper-distance DRC on the slots [this step, exporting multiple outline =
<br />layers, is already possible, if an export naming style is selected th=
at <br />doesn't result in overwriting the same file twice]<br /><br />Opti=
on B:<br /><br />after the subcircuit upgrade, next target will be pad stac=
ks=2E I am tempted <br />to introduce &quot;hole shapes&quot;: for a common=
 via or pin you'd use a circular <br />hole (drill) but it would also allow=
 lines for slots=2E This way the <br />resulting construct is like a via (p=
in) in all regards=2E According to my <br />current plans I will probably s=
tart coding pad stacks this year; having <br />non-circular hole is a small=
ish task compared to the rest pad stacks need, <br />so it's rather probabl=
e that we have this=2E In this setup the slots would <br />end up in the pl=
ated drill file, much like your example showed=2E<br /><br /><br /><br />No=
te: eventually both methods will be available=2E The only question is <br /=
>when, which also depends on how much pull they get from active pcb-rnd <br=
 />users=2E At the moment pad stack seems to be the one that would be <br /=
>implemented first=2E<br /><br />Regards,<br /><br />Igor2<br /><br /><br /=
></pre></blockquote></div></body></html>
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