X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Date: Mon, 3 Apr 2017 01:55:21 -0400 From: al davis To: geda-user AT delorie DOT com Subject: Re: [geda-user] Gnucap and Google summer of code. Message-ID: <20170403015521.7f0c4509@floyd.freeelectron.net> In-Reply-To: References: <20170330125608 DOT 7d04622a AT floyd DOT freeelectron DOT net> <20170402235928 DOT 7143c5f4 AT floyd DOT freeelectron DOT net> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Mon, 3 Apr 2017 06:30:21 +0200 (CEST) gedau AT igor2 DOT repo DOT hu wrote: > This looks like a netlist, I couldn't find a geometry description section. > > >From pcb-rnd we can export two things: For a full simulation, we need both, combined. > - geometry of the board: layers of traces, polygons, vias (the actual > 2d geometry, and _not_ parasitics, capacitance, resistance, etc. values) That is parameters on the "net". > - the abstract netlist we worked from; but this won't have any info about > vias, traces, layers, materials - you just get back the input netlist that > you have exported from the schematics editor (tinycad, kicad, gschem, > ltspice, mentor graphics). In this setup all we do would be a netlist > syntax conversion. We could do this, but I think it wouldn't be a big step > forward in hooking up pcb edition with simulation. The devices, what looks spice-ish to you, correspond to the footprints. The nets are the wires on the board. They can have parameters, like width, thickness, and length. A paramset or module defines what the net object is, and what parameters it has. Each instance would have things like length and width. The definition of net can define parameters like the stackup .. layers, insulator thickness, copper thickness. Length is determined by the "place" of the end points. Thickness is usually from the base model, the "stackup". Width can be either a net parameter or defined in the base. > Could you please show me an example on how your preferred format would > express the geometry? The geometry is expressed by the "place" objects. For now, how about: net #(.width(.5m)) aa (a1, a2); place (.$xposition(4m), .$yposition(4m)) place_a1 (a1); place (.$xposition(4m), .$yposition(14m)) place_a2 (a2); Dimensions are in meters. Suffix letters are supported, so 4m means 4 millimeters. One end of this net is at (4m, 4m), 4 mm right, 4 mm up from the reference point. The other end is at (4m, 10m) .. so it is 10 millimeters long. That is a net segment. For a complex net, encapsulate it: module net123 (a, b, c); net #(.width(.5m)) aaa01 (aaa1, aaa2); net #(.width(1.0m)) aaa02 (aaa2, aaa3); place (.$xposition(0), .$yposition(0m) place_aaa1 (aaa1); place (.$xposition(0), .$yposition(8m)) place_aaa2 (aaa2); place (.$xposition(10m), .$yposition(8m)) place_aaa3 (aaa3); // etc .. endmodule ... from the reference point, it goes 8 mm in y direction, then 10 mm in x direction. .. It's an "L" shaped trace. Then instantiate this instead of plain net: net123 a (a1, a2, a3); place (.$xposition(4m), .$yposition(14m)) place_a1 (a1); // this locates the (0,0) of net123 at (4m, 14m) This locates it so > And the good old question remains: what software would convert the pure > geometry to a netlist, extracting all the capacitance, resistance, etc. > values? Or is this the part the SoC project is for? One thing at a time .. For the first step, get it so the wires go point to point, with the correct end points. Then we will fill in the parameters.