On W= ed, Jan 18, 2017 at 2:40 PM, John Griessen (john AT ecosensory DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> w= rote:

On 01/18/2017 06:0= 3 AM, John Luciani (jluciani AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:

What type of stencil openings are you using?

I was thinking about .02mm more than the pad for the 0.5mm spacing pads 0.3= mm wide with a 0.2mm gap.

but then I read where all the mfrs want those pad rows to be one open recta= ngle.

I have about 0.7mm openings for each pad that overlap, so a better way to s= ay it
is the no mask area extends 0.2mm beyong the pads.

I am talking about the solder stencil o= penings not soldermask. With these small parts it is difficult

to maintain minimum soldermask widths.

=C2=A0

For the thermal pads I typical reduce the coverage to
between 50 - 70% (depending on the aperature dimensions).
The reduction is done using a layout similar to your footprint.
The spacing between the paste areas provides the channels.

I also reduce the coverage on the electrical pads.

The small ones around the edge?

Yes. I am talking about solder coverag= e not mask.

For these small parts there is little if any mask= left.

=C2=A0

I am going with a 9 pad grid in the center like the upper right of

http://ecosensory.com/geda/qfn_lands_problem.pn= g

but with the mask opening like in the lower right.=C2=A0 (No mask under edg= e, no separation of center and edge row pads
but for lack of metal.)

I'm planning on 4 center zone vias for heat and electrical contact.=C2= =A0 5 will only help stick it to the board.

Now that I think of it, I should probably drastically reduce the paste and = metal of the non-via connected ones
to let bubbles out even better.=C2=A0 It's not a high power app, just a= STM32F401CE.=C2=A0 The go ahead and put the vias
into the footprint also.=C2=A0 For now, I'll just place vias along with= parts and use the k key action command to resize pads.

Any hints on success appreciated.

I am suggesting a single= center copper pad on the PCB and multiple pads cut in the solder stencil. = All of the QFN

application notes I have read recommend simil= ar things. Checkout TI SLUA271A "QFN/SON Attachment" or

NXP SOT1189-1 footprint recommendation. There are a lot more notes out= there but these are the two I found quickly.

The TI datashe= ets usually have detailed recommendations.

For devices w= ith vias I add them to the footprint. For each device with a power pad I ma= ke a stencil footprint

with the same name but a sfp extension= . When making the stencil you can have a script replace footprints

with stencil footprints.

John L

=C2=A0

--
John Griessen -- building field gear for biologists
Ecosensory=C2=A0 Austin TX=C2=A0 ecosensory.com

http://www.wiblocks.com =C2=A0

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