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Subject: Re: [geda-user] Can an attribute be attached to text for later inclusion in gnetlist backend?
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From: John Doty <jpd AT noqsi DOT com>
In-Reply-To: <CAGde_xMDpUFy5P05Mg+zmzDtvbshvZAghR13F4UkSxxMqtw7yw@mail.gmail.com>
Date: Fri, 2 Sep 2016 08:39:59 -0400
Message-Id: <95E39BFD-E22B-4D51-A5A9-E4F4BB83C5FA@noqsi.com>
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On Sep 1, 2016, at 5:22 PM, Svenn Are Bjerkem =
(svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com] =
<geda-user AT delorie DOT com> wrote:

> I noted that the verilog back-end expects the attribute which define
> the name of the module to build a netlist for to be module-name and
> the vhdl back-end expects the attribute to be module_name. I don't
> know what the spice back-end expects.

I=92m not sure about the original spice back end.

spice-sdb uses a model-name attribute attached to a spice-subcircuit-LL =
block.

spice-noqsi can do it that way also, but I usually use a toplevel =
spice-prolog attribute containing a .subckt card. In spice-noqsi, you =
could have a toplevel attribute:

spice-prolog=3D.subckt module_name@ %io

This would pick up a toplevel module_name attribute and insert it in the =
prolog.

>=20
>>=20
>>>=20
>>> My main target is to just create top-level block-type schematics. I =
am
>>> not sure gnetlist could handle a "real" hierarchical design. I know
>>> too little about its capabilities.
>>>=20
>>=20
>> If I would know what is "real" hierarchical design... ;-) Yes,
>> gnetlist has many limitations, though it has some means for
>> working with hierarchical schematics.
>=20
> I find it hard to describe what makes a design a real hierarchical
> design other than that a symbol can represent a new schematic filled
> with symbols which again represent schematics. Kind of the way scheme
> works recursively into its problem solution. geda users make
> hierarchical spice netlists all the time, so I am not sure what really
> is the snag with gnetlist here, but for my most frequent use-case, a
> schematic will be one level only where each symbol represent a file
> with vhdl code (or verilog).

gnetlist cannot assemble a hierarchical netlist by itself: it can only =
do one module at a time. But for SPICE the hierarchical netlist is just =
the concatenation of the module netlists. Easy Makefile job.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com



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