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From: "Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date: Sat, 27 Aug 2016 02:18:11 +0000
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Subject: Re: [geda-user] Microwave PCB layout simulation or How to eat all
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On Fri, Aug 26, 2016 at 9:15 PM, al davis <ad252 AT freeelectron DOT net> wrote:
> On Fri, 26 Aug 2016 21:45:00 +0200
> "Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com]"
> <geda-user AT delorie DOT com> wrote:
>> So basically you wish for a Hyperlynx exporter for pcb ;-)
>
> Good luck getting Mentor (owner of Hyperlynx) to do that.

Someone has already written an open source hyperlynx importer for
openems. It stands that we could work off of that or ask them were
they got documentation for it.

Also OpenEMS supports other formating. Hyperlynx was just used in one example.

> What you really need is an exporter to gnucap-Verilog, or a plugin for
> gnucap to read (and write) the pcb format.
>
> If somebody wants to write that gnucap plugin, I will help you do it.
>

How does gnucap-verilog solve this? I thought verilog was just another
language for describing netlists and schematic behavior. How does that
get us closer to testing a pcb level implementation of a Wilkinson
splitter or a distributed element filter? I would think we would need
FEM of some kind to extract the relevant properties of the layout and
then process them for conversion into verilog?

I am not trying to be snotty I really respect your work on gnucap. I
just don't understand something.

-- 
Home
http://evanfoss.googlepages.com/
Work
http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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