On Tue, Aug 2, 2016 at 11:56 AM, John Doty <jpd AT noqsi DOT com> w= rote:

On Aug 2, 2016, at 2:18 PM, Ouabache Design= works (z3qmtr45 AT gma= il.com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

On Tue, Aug 2, 2016 at 10:27 AM, John Doty <jpd AT noqsi DOT com= > wrote:

On Aug 2, 2016, at 11:55 AM, Ouabache Des= ignworks (z3qmtr45@= gmail.com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

This gro= up has shown almost no interest in features that are needed by IC designers= if they are not also needed by PCB designers.

What do you imagine IC designers need? I design m= ixed-signal ASICs in gschem, and do not perceive any limits. Just another a= pplication for a complete, general purpose network topology editor.

John Doty=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0Noqsi Aerospace, Ltd.
http://= www.noqsi.com/
jpd AT noqsi DOT com

How about libraries that you can download that= don't have naming collisions with other libraries?

Since you have complete control of your libr= ary path, why is this a problem? Just put together the library *your* proje= ct needs. No big deal. Certainly not something that requires a new *feature= *.

So I need part A from Library foo and part B from library bar wh= en both libs have both parts. How do I set up the search path?

=C2=A0

=

How about c= omplete hierarchical design support with uniquification?

I=E2=80=99m not sure what your problem is. = My ASICs are hierarchical (of course).

When I descend down into a component instance then I want to see th= e schematic using all the elaborated values instead of the attribute names.=

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How about Busses? IC's need support for wires,vectors and busses.= Gschem does wires with some graphic support for vectors but nothing for bu= sses.

Need? Maybe they wo= uld be nice, but I haven=E2=80=99t really missed them. Mostly you want them= in complex digital parts, I think. If that was the kind of chip I was doin= g, I=E2=80=99d do those straight in HDL, not draw them in gschem. In any ca= se, there=E2=80=99s nothing preventing you giving a net a name that describ= es a bus, and dealing with that downstream.

=

Wires and vectors h= ave inputs and outputs. Busses have masters and slaves.=C2=A0 You need to s= upport bundling wires,vectors and busses into bigger busses, passing it up = and down hierarchies and then splitting everything back apart at the end.

Even if you do hdl you still want to do your top levels in= schematics because that is your documentation and will be in sync with
=

the design.

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Gschem supports small data designs. IC designe= rs need support for big data projects.

Big data designs are sanely composed of small data compo= nents. Gschem handles those small data components well. Drawings don=E2=80= =99t scale well to big data, so gschem isn=E2=80=99t the right tool for the= higher levels (which are more like programming than graphical design).

We used to design ICs us= ing schematic capture until verilog came along. Then the architects switche= d from using schematics to Microsoft Visio. It was a giant step backwards.<= br>

=C2=A0

John Eaton

John Doty=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0<= /span>Noqsi Aerospace, Ltd.
http://ww= w.noqsi.com/
jpd AT noqsi DOT com