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        Mon, 01 Aug 2016 09:50:17 -0700 (PDT)
Date: Mon, 1 Aug 2016 18:50:15 +0200
From: "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] Wilkinson splitter - how to implement and use?
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> >Dear Members,
> >
> >I need to design a RF board with some Wilkinson splitters on it. While the
> >symbol of splitter is ready (rf/splitter-1.sym) and for pcb we have even a
> >java generator
> >(https://github.com/erichVK5/WilkinsonPowerDividerFootprintGenerator), I'm
> >not sure how to use it. The splitter is just a few fancy tracks on pcb (plus
> >a resistor) that in fact are all connected. In schematics however this is an
> >element with 3 pins. In pcb I can not name the splitter pins "1", "2", "3",
> >because this will give warnings about shorted nets. If I change schematics
> >symbol (short its pins) there will be no warnings but all RF nets are
> >reduced to one - that is not the case (all splitter input/output connections
> >are lost).
> >
> >Is there a better/preferred way to deal with such RF components in gEDA?
> >Thanks in advance,
> >Michael Widlok
> >
> 
> In pcb-rnd I see an ugly workaround for this: two footprints. One 
> normal footprint with 3 separate terminals, so the netlist can ensure you 
> connect the right things to the right places. Another footprint with a 
> "track drawn of pads" (hack), marked as "nonetlist", placed on top of the 
> first footprint. This would physically connect the three terminals, on 
> copper, but because of the nonetlist flag pcb-rnd would still think 
> there's no connection (DRC-wise).

No problem. Ordinary copper on pins but nonetlist flag in between. There may be need to add extra overlapping copper with and without flag.

> 
> Regards,
> 
> Igor2