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X-Envelope-From: hsank AT nospam DOT chipforge DOT org
X-Envelope-To: <geda-user AT delorie DOT com>
Date: Sat, 12 Mar 2016 14:56:47 +0100
Message-ID: <20160312145647.Horde.toH7mUmRASGNT3axa-gppQG@webmail.in-berlin.de>
From: Hagen SANKOWSKI <hsank AT nospam DOT chipforge DOT org>
To: geda-user AT delorie DOT com
Subject: [geda-user] gnetlist shorting wires
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Content-Type: text/plain; charset=utf-8; format=flowed; DelSp=Yes
Content-Disposition: inline


Hello.

I use geda/gaf gschem 1.8.2. under Debian 8.3 and still fighting  
against some shortings, which gnetlist put into my netlist before  
running PCB.
A small example is attached with a own symbol for the ADG738 - SPI  
controled switch - and the schematic around them.

During gnetlist generation I got this lines, which seems to be important:

   Found duplicate net name, renaming [INPUT] to [\_SPIR_CS\_]
   Found duplicate net name, renaming [OUTPUT] to [SPIR_SDO]
   Found duplicate net name, renaming [S1] to [B]
   Found duplicate net name, renaming [IO] to [B]

Well, I investigate via -i interactive session, that this lines  
already printed during read-into-memory, before hand over the design  
to the backend.

In the Verilog Netlist (okay, Verilog is what I understand best as an  
Chip Designer) e.g. I see this bullshit

   A A (
     .\1  ( B ),
     .A ( A )
     );
   \\_RESET\_  \\_RESET\_  (
     .\1  ( \\_SPIR_CS\_  ),
     .\\_RESET\_  ( \\_RESET\_  )
     );
   SCLK SCLK (
     .\1  ( \\_SPIR_CS\_  ),
     .SCLK ( SCLK )
     );
   SPIR_SDI SPIR_SDI (
     .\1  ( \\_SPIR_CS\_  ),
     .SPIR_SDI ( SPIR_SDI )
     );

which IMHO it should be

   A A (
     .\1  ( A ),
     .A ( A )
     );
   \\_RESET\_  \\_RESET\_  (
     .\1  ( \\_SPIR_RESET\_  ),
     .\\_RESET\_  ( \\_RESET\_  )
     );
   SCLK SCLK (
     .\1  ( \\_SCLK  ),
     .SCLK ( SCLK )
     );
   SPIR_SDI SPIR_SDI (
     .\1  ( SPIR_SDI  ),
     .SPIR_SDI ( SPIR_SDI )
     );

So what I might doing wrong? Or where can I see the Source Code for  
this read-into-memory inside gnetlist to verify am I an idiot or  
getting a tool bug?

Best regards,
Hagen

-- 
"They who can give up essential liberty to obtain a little temporary
safety, deserve neither liberty nor safety." Benjamin Franklin (1775)

--=_Sbvisgo5NGmTSPZL9H2obp5
Content-Type: text/plain; name=ADG738_TSSOP16.sym
Content-Disposition: attachment; size=6607; filename=ADG738_TSSOP16.sym

v 20110115 2
##      ******************************************************************
##
##      Organisation:   Chipforge
##                      Germany / European Union
##
##      Profile:        Chipforge focus on fine System-on-Chip Cores in
##                      Verilog HDL Code which are easy understandable and
##                      adjustable. For further information see
##                              www.chipforge.org 
##                      there are projects from small cores up to PCBs, too.
##
##      File:           A1ATE/Library/symbols/ADG738_TSSOP16.sym
##
##      Purpose:        gEDA and friends (gaf) Symbole file
##
##      ******************************************************************
##
##      //////////////////////////////////////////////////////////////////
##
##      Copyright (c) 2015 by
##                      SANKOWSKI, Hagen - hsank AT nospam DOT chipforge DOT org
##
##      This source file may be used and distributed without restriction
##      provided that this copyright statement is not removed from the
##      file and that any derivative work contains the original copyright
##      notice and the associated disclaimer.
##
##      This source is free software; you can redistribute it and/or modify
##      it under the terms of the GNU General Public License as published by
##      the Free Software Foundation; either version 2 of the License, or
##      (at your option) any later version.
##
##      This source is distributed in the hope that it will be useful,
##      but WITHOUT ANY WARRANTY; without even the implied warranty of
##      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
##      GNU General Public License for more details.
##
##        (__)  You should have received a copy of the GNU General Public
##        oo )  License along with this program; if not, write to the
##        /_/|  Free Software Foundation Inc., 51 Franklin St., 5th Floor,
##              Boston, MA 02110-1301, USA
##
##      //////////////////////////////////////////////////////////////////
#
#
##      ------------------------------------------------------------------
##                      ANNOTATIONS
##      ------------------------------------------------------------------
##
T 300 100 5 10 1 1 0 0 1
device=ADG738_TSSOP16
T 300 3600 8 10 1 1 0 0 1
refdes=U?
T 300 4150 5 10 0 0 0 0 1
footprint=TSSOP16
T 300 3950 5 10 0 0 0 0 1
numslots=0
T 0 0 5 10 0 0 0 0 1
description=CMOS, Low Voltage, 3-Wire Serially-Controlled, Matrix Switches
T 0 300 5 10 0 0 0 0 1
documentation=http://www.analog.com/media/en/technical-documentation/data-sheets/ADG738_739.pdf
T 300 4950 5 10 0 0 0 0 1
author=SANKOWSKI, Hagen <hsank AT nospam DOT chipforge DOT org>
##      ------------------------------------------------------------------
##                      DEFINITIONS
##      ------------------------------------------------------------------
#
##      symbol box
#
B 300 300 2000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
#
##      pins - right side, down-wards
#
P 2300 3300 2600 3300 1 0 1
{
T 2400 3350 5 8 1 1 0 0 1
pinnumber=9
T 2400 3250 5 8 0 1 0 2 1
pinseq=1
T 2250 3300 9 8 1 1 0 6 1
pinlabel=S8
T 2250 3300 5 8 0 1 0 8 1
pintype=io
}
P 2300 2900 2600 2900 1 0 1
{
T 2400 2950 5 8 1 1 0 0 1
pinnumber=10
T 2400 2850 5 8 0 1 0 2 1
pinseq=2
T 2250 2900 9 8 1 1 0 6 1
pinlabel=S7
T 2250 2900 5 8 0 1 0 8 1
pintype=io
}
P 2300 2500 2600 2500 1 0 1
{
T 2400 2550 5 8 1 1 0 0 1
pinnumber=11
T 2400 2450 5 8 0 1 0 2 1
pinseq=3
T 2250 2500 9 8 1 1 0 6 1
pinlabel=S6
T 2250 2500 5 8 0 1 0 8 1
pintype=io
}
P 2300 2100 2600 2100 1 0 1
{
T 2400 2150 5 8 1 1 0 0 1
pinnumber=12
T 2400 2050 5 8 0 1 0 2 1
pinseq=4
T 2250 2100 9 8 1 1 0 6 1
pinlabel=S5
T 2250 2100 5 8 0 1 0 8 1
pintype=io
}
P 2300 1700 2600 1700 1 0 1
{
T 2400 1750 5 8 1 1 0 0 1
pinnumber=7
T 2400 1650 5 8 0 1 0 2 1
pinseq=5
T 2250 1700 9 8 1 1 0 6 1
pinlabel=S4
T 2250 1700 5 8 0 1 0 8 1
pintype=io
}
P 2300 1300 2600 1300 1 0 1
{
T 2400 1350 5 8 1 1 0 0 1
pinnumber=6
T 2400 1250 5 8 0 1 0 2 1
pinseq=6
T 2250 1300 9 8 1 1 0 6 1
pinlabel=S3
T 2250 1300 5 8 0 1 0 8 1
pintype=io
}
P 2300 900 2600 900 1 0 1
{
T 2400 950 5 8 1 1 0 0 1
pinnumber=5
T 2400 850 5 8 0 1 0 2 1
pinseq=7
T 2250 900 9 8 1 1 0 6 1
pinlabel=S2
T 2250 900 5 8 0 1 0 8 1
pintype=io
}
P 2300 500 2600 500 1 0 1
{
T 2400 550 5 8 1 1 0 0 1
pinnumber=4
T 2400 450 5 8 0 1 0 2 1
pinseq=8
T 2250 500 9 8 1 1 0 6 1
pinlabel=S1
T 2250 500 5 8 0 1 0 8 1
pintype=io
}
#
##      pins - left side, down-wards
#
V 250 3300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 3300 200 3300 1 0 0
{
T 200 3350 5 8 1 1 0 6 1
pinnumber=16
T 200 3250 5 8 0 1 0 8 1
pinseq=9
T 350 3300 9 8 1 1 0 0 1
pinlabel=\_SYNC\_
T 350 3300 5 8 0 1 0 2 1
pintype=in
}
P 0 2900 300 2900 1 0 0
{
T 200 2950 5 8 1 1 0 6 1
pinnumber=15
T 200 2850 5 8 0 1 0 8 1
pinseq=10
T 350 2900 9 8 1 1 0 0 1
pinlabel=DOUT
T 350 2900 5 8 0 1 0 2 1
pintype=out
}
P 0 2500 300 2500 1 0 0
{
T 200 2550 5 8 1 1 0 6 1
pinnumber=3
T 200 2450 5 8 0 1 0 8 1
pinseq=11
T 350 2500 9 8 1 1 0 0 1
pinlabel=DIN
T 350 2500 5 8 0 1 0 2 1
pintype=in
}
P 0 2100 300 2100 1 0 0
{
T 200 2150 5 8 1 1 0 6 1
pinnumber=1
T 200 2050 5 8 0 1 0 8 1
pinseq=12
T 350 2100 9 8 1 1 0 0 1
pinlabel=SCLK
T 350 2100 5 8 0 1 0 2 1
pintype=clk
}
V 250 1300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 1300 200 1300 1 0 0
{
T 200 1350 5 8 1 1 0 6 1
pinnumber=2
T 200 1250 5 8 0 1 0 8 1
pinseq=13
T 350 1300 9 8 1 1 0 0 1
pinlabel=\_RESET\_
T 350 1300 5 8 0 1 0 2 1
pintype=in
}
P 0 500 300 500 1 0 0
{
T 200 550 5 8 1 1 0 6 1
pinnumber=8
T 200 450 5 8 0 1 0 8 1
pinseq=14
T 350 500 9 8 1 1 0 0 1
pinlabel=D
T 350 500 5 8 0 1 0 2 1
pintype=io
}
#
##      pins - upper side, clock-wise
#
P 1700 3500 1700 3800 1 0 1
{
T 1600 3800 5 8 1 1 90 7 1
pinnumber=13
T 1800 3600 5 8 0 0 90 7 1
pinseq=15
T 1700 3400 9 8 1 1 90 7 1
pinlabel=VDD
T 1800 3400 5 8 0 1 90 7 1
pintype=pwr
}
#
##      pins - down side, counter clock-wise
#
P 1300 300 1300 0 1 0 1
{
T 1200 0 5 8 1 1 90 1 1
pinnumber=14
T 1400 0 5 8 0 0 90 7 1
pinseq=16
T 1300 400 9 8 1 1 90 1 1
pinlabel=GND
T 1400 400 5 8 0 1 90 7 1
pintype=pwr
}
##
##            ;;        .;;;. ;; ;; ;; ;;;;. ;;;; ;;;. ;;;;. .;;;. ;;;;
##            ;;;;;;    ;; ;; ;; ;; ;; ;; ;; ;;  ;; ;; ;; ;; ;; ;; ;;
##         ;, ;;        ;;    ;;;;; ;; ;; ;; ;;; ;; ;; ;;;;' ;;,,, ;;;
##      ;;;;;;;;;;;;    ;; ;; ;; ;; ;; ;;;;' ;;  ;; ;; ;;';; ;; ;; ;;
##         :' ;;        ';;;' ;; ;; ;; ;;    ;;  ';;;' ;; ;; ';;;; ;;;;
##
##      ************    Revision History        **************************
##
##      $Log$
##      ******************************************************************

--=_Sbvisgo5NGmTSPZL9H2obp5
Content-Type: text/x-fortran; name=A1ATE-R-Bridge_ES0.sch
Content-Disposition: attachment; size=6004; filename=A1ATE-R-Bridge_ES0.sch

v 20130925 2
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{
T 53500 39400 5 10 1 1 0 0 1
date=2015-07-09
T 57400 39400 5 10 1 1 0 0 1
rev=ES0
T 57400 39100 5 10 1 1 0 0 1
auth=SANKOWSKI, Hagen
T 53500 39700 5 10 1 1 0 0 1
fname=./A1ATE/Sources/schematics/A1ATE-R-Bridge_ES0.sch
T 56800 40100 5 14 1 1 0 4 1
title=ATE-Shield 'Arduino uno' - One R-Bridge per PIN -- ADG738
}
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N 56000 44400 59800 44400 4
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}
N 56000 44800 56900 44800 4
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T 56000 44800 5 10 1 1 0 0 1
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N 56000 45200 56900 45200 4
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T 56000 45200 5 10 1 1 0 0 1
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N 56000 45600 56900 45600 4
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T 56000 45600 5 10 1 1 0 0 1
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}
N 56000 46000 56900 46000 4
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T 56000 46000 5 10 1 1 0 0 1
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}
N 56000 46400 56900 46400 4
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T 56000 46400 5 10 1 1 0 0 1
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}
N 56000 46800 56900 46800 4
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T 56000 46800 5 10 1 1 0 0 1
netname=S7
}
N 56000 47200 56900 47200 4
{
T 56000 47200 5 10 1 1 0 0 1
netname=S8
}
C 49900 47100 1 0 0 input-2.sym
{
T 49900 47100 5 10 0 0 0 0 1
net=\_SPIR_CS\_:\_SPIR_CS\_
T 49900 47100 5 10 0 0 0 0 1
device=\_SPIR_CS\_
T 49900 47100 5 10 0 0 0 7 1
value=\_SPIR_CS\_
T 49900 47100 5 10 1 0 0 0 1
refdes=\_SPIR_CS\_
}
C 49900 46300 1 0 0 input-2.sym
{
T 49900 46300 5 10 0 0 0 0 1
net=SPIR_SDI:SPIR_SDI
T 49900 46300 5 10 0 0 0 0 1
device=SPIR_SDI
T 49900 46300 5 10 1 1 0 7 1
value=SPIR_SDI
T 49900 46300 5 10 1 0 0 0 1
refdes=SPIR_SDI
}
C 49900 45900 1 0 0 input-2.sym
{
T 49900 45900 5 10 0 0 0 0 1
net=SCLK:SCLK
T 49900 45900 5 10 0 0 0 0 1
device=SCLK
T 49900 45900 5 10 1 1 0 7 1
value=SCLK
T 49900 45900 5 10 1 0 0 0 1
refdes=SCLK
}
C 51300 46900 1 180 0 output-2.sym
{
T 51300 46900 5 10 0 1 180 0 1
net=SPIR_SDO:SPIR_SDO
T 51300 46900 5 10 0 0 180 0 1
device=SPIR_SDO
T 51300 46900 5 10 1 1 180 1 1
value=SPIR_SDO
T 51300 46900 5 10 1 0 0 0 1
refdes=SPIR_SDO
}
N 51300 47200 53400 47200 4
{
T 51300 47200 5 10 1 1 0 0 1
netname=\_SPIR_CS\_
}
N 51300 46800 53400 46800 4
{
T 51300 46800 5 10 1 1 0 0 1
netname=SPIR_SDO
}
N 51300 46400 53400 46400 4
{
T 51300 46400 5 10 1 1 0 0 1
netname=SPIR_SDI
}
N 51300 46000 53400 46000 4
{
T 51300 46000 5 10 1 1 0 0 1
netname=SCLK
}
N 55100 48000 55100 47700 4
{
T 55100 48000 5 10 1 1 0 0 1
netname=Vcc
}
C 54600 42900 1 0 0 gnd-1.sym
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T 54600 42900 5 10 0 0 0 0 1
net=GND:GND
}
N 54700 43900 54700 43200 4
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T 54700 43900 5 10 1 1 0 0 1
netname=GND
}
C 49900 45100 1 0 0 input-2.sym
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T 49900 45100 5 10 0 0 0 0 1
net=\_RESET\_:\_RESET\_
T 49900 45100 5 10 0 0 0 0 1
device=\_RESET\_
T 49900 45100 5 10 1 1 0 7 1
value=\_RESET\_
T 49900 45100 5 10 1 0 0 0 1
refdes=\_RESET\_
}
N 51300 45200 53400 45200 4
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T 51300 45200 5 10 1 1 0 0 1
netname=\_RESET\_
}
C 53400 43900 1 0 0 ADG738_TSSOP16.sym
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T 53700 44000 5 10 1 1 0 0 1
device=ADG738_TSSOP16
T 53700 47500 5 10 1 1 0 0 1
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T 53700 48050 5 10 0 0 0 0 1
footprint=TSSOP16
}
N 51300 44400 53400 44400 4
{
T 51300 44400 5 10 1 1 0 0 1
netname=A
T 51300 44400 5 10 1 1 0 0 1
netname=A
}
C 56900 44700 1 0 0 resistor-2.sym
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T 57300 45050 5 10 0 0 0 0 1
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T 57100 45000 5 10 1 1 0 0 1
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T 57100 44700 5 10 1 1 0 0 1
value=147
T 56900 44700 5 10 0 0 0 0 1
footprint=0805
}
C 56900 45500 1 0 0 resistor-2.sym
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T 57300 45850 5 10 0 0 0 0 1
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T 57100 45800 5 10 1 1 0 0 1
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T 57100 45500 5 10 1 1 0 0 1
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T 56900 45500 5 10 0 0 0 0 1
footprint=0805
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C 56900 46300 1 0 0 resistor-2.sym
{
T 57300 46650 5 10 0 0 0 0 1
device=RESISTOR
T 57100 46600 5 10 1 1 0 0 1
refdes=RR6
T 57100 46300 5 10 1 1 0 0 1
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T 56900 46300 5 10 0 0 0 0 1
footprint=0805
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C 56900 47100 1 0 0 resistor-2.sym
{
T 57300 47450 5 10 0 0 0 0 1
device=RESISTOR
T 57100 47400 5 10 1 1 0 0 1
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T 57100 47100 5 10 1 1 0 0 1
value=147k
T 56900 47100 5 10 0 0 0 0 1
footprint=0805
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T 57300 48700 8 10 1 0 90 4 1
RR2..RR8: E96, 1%
C 56900 45100 1 0 0 resistor-2.sym
{
T 57300 45450 5 10 0 0 0 0 1
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T 57100 45400 5 10 1 1 0 0 1
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T 57100 45100 5 10 1 1 0 0 1
value=681
T 56900 45100 5 10 0 0 0 0 1
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C 56900 45900 1 0 0 resistor-2.sym
{
T 57300 46250 5 10 0 0 0 0 1
device=RESISTOR
T 57100 46200 5 10 1 1 0 0 1
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T 57100 45900 5 10 1 1 0 0 1
value=6k81
T 56900 45900 5 10 0 0 0 0 1
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{
T 57300 47050 5 10 0 0 0 0 1
device=RESISTOR
T 57100 47000 5 10 1 1 0 0 1
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T 57100 46700 5 10 1 1 0 0 1
value=68k1
T 56900 46700 5 10 0 0 0 0 1
footprint=0805
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N 57800 47200 58500 47200 4
N 58500 47200 58500 44400 4
{
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netname=B
}
N 57800 46800 58500 46800 4
N 57800 46400 58500 46400 4
N 57800 46000 58500 46000 4
N 57800 45600 58500 45600 4
N 57800 45200 58500 45200 4
N 57800 44800 58500 44800 4
T 60800 39000 9 10 1 0 90 0 1
Resistor Network
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T 50900 41800 5 10 0 0 0 0 1
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C 51200 42300 1 90 0 capacitor-1.sym
{
T 50500 42500 5 10 0 0 90 0 1
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T 50700 42500 5 10 1 1 90 0 1
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T 50300 42500 5 10 0 0 90 0 1
symversion=0.1
T 51100 42900 5 10 1 1 0 0 1
value=100n
T 51200 42300 5 10 0 0 0 0 1
footprint=1206
}
N 51000 43400 51000 43200 4
{
T 51000 43400 5 10 1 1 0 0 1
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netname=GND
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}
C 54900 48000 1 0 0 generic-power.sym
{
T 55100 48250 5 10 1 1 0 3 1
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}
C 50800 43400 1 0 0 generic-power.sym
{
T 51000 43650 5 10 1 1 0 3 1
net=Vcc:Vcc
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C 59800 44300 1 0 0 io-1.sym
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T 59800 44300 5 10 1 0 0 0 1
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T 59800 44300 5 10 0 0 0 0 1
device=B
T 59800 44300 5 10 1 1 0 1 1
value=B
T 59800 44300 5 10 1 0 0 0 1
refdes=B
}
C 51300 44500 1 180 0 io-1.sym
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T 51300 44500 5 10 1 0 180 0 1
net=A:A
T 51300 44500 5 10 0 0 180 0 1
device=A
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value=A
T 51300 44500 5 10 1 0 0 0 1
refdes=A
}

--=_Sbvisgo5NGmTSPZL9H2obp5--