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From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=)
To: <geda-user AT delorie DOT com>
Subject: Re: [geda-user] pcb import schematic crash, parantheses in netname
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Date: Tue, 16 Feb 2016 21:15:04 +0100
In-Reply-To: <CAJXU7q_wm_jqACf6ycg4bVRPRKx53xUKq9iGCLhP=k-C_LjepA@mail.gmail.com>
	(Peter Clifton's message of "Tue, 16 Feb 2016 18:32:42 +0000")
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"Peter Clifton (petercjclifton AT googlemail DOT com) [via
geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:

> Bonus points if the quoting / escaping scheme is standard w.r.t. other
> programs / common usage.

Like Verilog?  Since Verilog is a netlist format that is used in a
lot of different flows, it accepts any characters in identifiers, except
whitespace.

> Escaped identifiers allow for any printable ASCII character to be
> included in the name. Escaped identifiers begin with white space. The
> backslash (“\”) character leads off the identifier, which is then
> terminated with white space. The leading backslash character is not
> considered part of the identifier.

-- 
Stephan