X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=) To: "Nicklas Karlsson \(nicklas.karlsson17\@gmail.com\) \[via geda-user\@delorie.com\]" Subject: Re: [geda-user] The nature of gEDA layers References: <20160126233332 DOT dec2f06f5c74354a3841989c AT gmail DOT com> <20160127091746 DOT 1c7a976c2752f913921688ac AT gmail DOT com> <20160127141334 DOT c738feb9dbeb54a7dec3dff8 AT gmail DOT com> <56A8F74B DOT 8080304 AT ecosensory DOT com> <56A961BC DOT 3040405 AT ecosensory DOT com> <56A9E416 DOT 8080500 AT ecosensory DOT com> <20160128124020 DOT 8f2f33210481f637a696f5d0 AT gmail DOT com> <20160128164922 DOT 7bd920859ab8462f8abb0f40 AT gmail DOT com> <20160128191943 DOT d3f06f258e112a8d7d532327 AT gmail DOT com> Date: Thu, 28 Jan 2016 22:13:55 +0100 In-Reply-To: <20160128191943.d3f06f258e112a8d7d532327@gmail.com> (Nicklas Karlsson's message of "Thu, 28 Jan 2016 19:19:43 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" writes: > Geometry of plating between layers depnend on cut out shape which as > is now is a drilled hole and it is no problem to figure out shape of > plating on board layer. The other direction to draw cut out on board > layer and plating between layer on separate layer with same mechanical > position is not hard to implement but require drawing primitives on > board and plating layer to agree. > >> Why is the inter-layer connectivity a fundamentally different different >> idea? > > Because drawing primitives added to the inter layer conectivity must > match board cut out edges. You still want to model a 3D PCB accurately. But that is not the job of the layout program and its core data structures. For reliable PCB design and production we need transparency, not a lot of under the hood modeling. The drill holes are not part of the board shape. The manufacturer need a drill file, and Gerbv shows those as a layer with circles. Since that is something the layout program naturally does, the drills shall be represented as such a layer with circles on it. And if the layer has attributes which tell that it cunductivly connects to certain copper layers, the code that figures out connectivity as implememted knows to traverse layers in the same way it follows a sequence of lines. Nothing special. > I think you think drilling of plated hole or plated cut out is the > inter layer connectivity which in sort of is correct regarding > connectivity. I thing that the drillfile(s) will be generated from the via-planes quite transparently, with little margin of uncertainty for the user. > I think drilling is cut out at least on the board layer(s) and plating > is adding of conductive material at same mechanical position as board > layer. The layout process does not care at all about how that circle that we think about as via hole is implemented by the manufacturer. Not at all. > That a drilled hole is a cut out at least in board layer(s) is no > problem. I however think the most appropiate for most cases would be > to derive connectivity between layer from the plated cut outs. That is exaclty what the drill layer is. A layer to draw plated cutouts on. > This is close to what happens now then a plated via/pin is assumed to > connect all layers although these connections do not end up as drawing > primitives on a layer. The drill layer does not draw on copper layers. The copper layers must have their own copper object at the same position, that the plated hole can connect to. Let me draw an example of how I see a via: A layout with four copper layers, including a gnd plane on an inner layer, and a via with 16mil drill, 10mil annulus on the outer layers and 8mil annulus on the inner layers, "+" thermals on the GND plane. Layer{name="Vias", connects=("Top", "Mid", "GND", Bot"), Attributes{conductive, elements="THROUGHHOLES"}} Layer{name="Top", connects=("Vias"), Attributes{conductive, elements="COMPONENTSIDE"}} Layer{name="Mid", connects=("Vias"), Attributes{conductive, elements="INNER"}} Layer{name="GND", connects=("Vias"), Attributes{conductive, elements="INNER", planeclearance=8mil}} Layer{name="Bot", connects=("Vias"), Attributes{conductive, elements="SOLDERSIDE"}} Layer{name="Top:mask", Attributes{elements="COMPONENTSIDE:mask"}} Layer{name="Bot:mask", Attributes{elements="SOLDERSIDE:mask"}} Layer{name="milling", Attributes{outline}} Line{layer="milling", width=1mil, Points{(0,0),(0,1000mil),(1000mil,1000mil),(1000mil,0),(0,0)}} Polygon { layer="GND", depth=500, Points{(20mil,20mil), (20mil,990mil), (990mil,990mil), (990mil,20mil)} } # a unplaced Via library object (no origin=) Group { name="via:signalrouting", Attributes{via="signalrouting"}, Line {layer="Vias", width=16mil, Points{(0,0)}, } Line {layer="Top", width=36mil, depth=100, Points{(0,0)}, } Line {layer="Top", width=56mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, } Line {layer="Top:mask", width=42mil, depth=-100, Points{(0,0)}, } Line {layer="Mid", width=32mil, depth=100, Points{(0,0)}, } Line {layer="Mid", width=48mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, } Line {layer="GND", width=32mil, depth=100, Points{(0,0)}, } Line {layer="GND", width=48mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, } Line {layer="Bot", width=36mil, depth=100, Points{(0,0)}, } Line {layer="Bot:mask", width=42mil, depth=-100, Points{(0,0)}, } } Group { origin=(x,y), Group{ref="via:signalrouting", origin=(0,0)} Line {layer="GND", width=8mil, depth=200, Points{(0,-50mil), (0,50mil)}, Attributes{thermal="plus"}, } Line {layer="GND", width=8mil, depth=200, Points{(-50mil,0), (50mil,0)}, Attributes{thermal="plus"}, } } -- Stephan