X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Message-ID: <569E636F.3040305@iee.org> Date: Tue, 19 Jan 2016 16:25:19 +0000 From: "M. J. Everitt (m DOT j DOT everitt AT iee DOT org) [via geda-user AT delorie DOT com]" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: geda-user AT delorie DOT com Subject: Re: [geda-user] pcb loop paste buffer, renumber (first multi channel design) References: <20151021192359 DOT 3dd8ad6d253c781da5523554 AT gmail DOT com> <201510211839 DOT t9LIdVcv027165 AT envy DOT delorie DOT com> <20151021222506 DOT 79643602de30ad2dd5541165 AT gmail DOT com> <20151022115247 DOT 3c1c2f13 AT akka> <20151022123903 DOT dddb6c83fa5a3db0963f4162 AT gmail DOT com> <201510221641 DOT t9MGfxJq003243 AT envy DOT delorie DOT com> <20151022212642 DOT abe0686f3bb04a3067667c43 AT gmail DOT com> <201510221951 DOT t9MJpjgA013544 AT envy DOT delorie DOT com> <562951C5 DOT 2010500 AT xs4all DOT nl> <562B531C DOT 5090004 AT xs4all DOT nl> <20160118171041 DOT 60f9ff0fd41a668af0fa84f4 AT gmail DOT com> <569D3751 DOT 2020402 AT xs4all DOT nl> <569D4266 DOT 7000905 AT prochac DOT sk> <20160119135636 DOT 8b2397941a5d4c4f48c9a626 AT gmail DOT com> <569E3532 DOT 2000701 AT iee DOT org> <20160119145802 DOT 81daa1f66cbb5cfebbba834c AT gmail DOT com> <569E4CE9 DOT 6030900 AT iee DOT org> In-Reply-To: Content-Type: multipart/alternative; boundary="------------000000050303050703070608" X-Provags-ID: V03:K0:uEAxnxoH+opgQQsHxaBJ3FggMrmo6ApghFeKyNLy+EF4ODGwncI pv1WdmAYjCTHOk4egPvFEQ6lVp6F9V2omIwJYAJBCkZkAEfdI4bA4OTf5y4+KmZBNNSQgTD JiCeFolB90j/qIlkk7qaeJ1j5cdRQ66My0rAc54aPkrgWjRVzGAuARCILvqhF34bWAaEMAL p/Md0SV5Qt3Dzsw5SWvzA== X-UI-Out-Filterresults: notjunk:1;V01:K0:xXH49zw1haM=:Pq/MQ8UbhFcINbb4RbTaiQ Ip+LD+wTlkoVE56j6+onPPewGx2xVQQeY6WUY9Xw3NWm5hgz52piW5DhRcDu2Xl33M/6TccQ7 OSgPQC8dTPPBNqWJpQ28lI+PHcZENjXMTK8aj1V6qoowBtUaphgiOJxBzg7oOzoKcY9zzo72w IM64M2WYlMEco02UUpLtrVGHJlQJ4IytMYeULmmBoshdycrYCwhN7AM3jBQt/P8YfPbtPUTFW btSwGvrod98c3UD/5uxWHkDY1A4pQV/pD0chEyYQDGJQTy4FelX/+/SdmJvlWikf2GL0YHsSc Lj/kyfaSjO6gyGnefVi8rMAc0EFANX0RIJ360OueGa2fjV0kea+TYwWeEcNgBxwrg5BxVa/hS IHfIny6ex5oGTQaVshXSkyNA5UkRUzDTcqxn8dyVd+n3cSIcpcMKxjz8oLbtLzsfmV4Q/URDo rfbNZzv/hjM5Jwlb4tT+9eIp+Io8GkMNvBDZ0jP9Yk9u5P/jk3rUU8/N1BBTvFxbDjDtXr7pG HGIUfP22QiRJ+8qodhR3/qKchmiATPFqBdIVZWszW6aYSnn4d6maDF6Tm1byBiOd7tJ7a27qj I8d//Tr7g0+F6eLHJp4g3IKg8MDxyRDWNAZttdLu7DZp6arNVCaumVARasw6EmlZ2vnVFwV+Y E9pIbxiVGJ1orvtdI6VoH43mb7nObN8EM2Do7tV+6g69vi20P+V1kYaWbuMLs7wXAhYs04IsP Buegdwo7tDqZpNDv4LaiHgPTzX0B3dk654+1liyCm5bt682FEe8GHnzLqiqPuHxhXvVqb3gei 0qyy6gkBfVl/UN/YOiZfPm72rQDIg== Reply-To: geda-user AT delorie DOT com This is a multi-part message in MIME format. --------------000000050303050703070608 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Think you've hit the nail on the head really here Peter, and you have better knowledge of the code than I ... On 19/01/16 15:53, Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] wrote: > > Really you need to have a reuse at the schematic level before you can > expect any intelligent behaviour in the pcb tool. > > I've done multi channel designs with hierarchical schematics before... > The rename just becomes X1/R1 -> X2/R1 etc... > > My rename plugin might still be floating about somewhere > "sedrename"... Now we've got more plugins committed with the main > repository, it might be fun to dig that one out and include it too... > Was very handy when your transformation between channels can be > expressed as a regex. > > The main downside with heirarchical refdes is the silkscreen and board > fab house. They HATED IT. Couldn't cope with the long heirarchical > refdes, didn't WANT to cope with the patch I applied to just put the > last heirarchical part on the silk by each part, but then drew boxes > manually with module designations. > > In the end, I used pcb's renumber feature to assign completely new > refdes on the board, but instead of back annotating (impossible as we > stand, with heirarchical schematics), I added a quick kludgy patch to > read back in the rename file, so pcb could map between the gnetlist > produced heirarchical netlist, and the flat refdes on the board. > > Made debugging extra fun, having to manually indirect from > heirarchical schematic refdes to on board refdes, but at least it > didn't upset the board assembly fab! > > I suppose I could also have post proceed out a flattened set of > schematics with the renamed refdes if that became useful. > > Peter > > On 19 Jan 2016 14:51, "M. J. Everitt (m DOT j DOT everitt AT iee DOT org > ) [via geda-user AT delorie DOT com > ]" > wrote: > > > On 19/01/16 13:58, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com > ) [via > geda-user AT delorie DOT com ] wrote: > >>> I tested and as far as I understand it works like this: > >>> x is old refdes number > >>> n increase with this value > >>> Rx --> Rx+n > >>> > >>> I have subsheets and numbers look like this: > >>> x is old refdes number > >>> n increase with this value > >>> want this S2/S1/Rx --> S2/S1+n/Rx > >>> but get this S2/S1/Rx --> S2/S1+n/Rx > >>> and the need is to change subsheet number and use this for > another channel. > >>> > >>> For rename to work reasonable well there must be an integer > difference between refdeses for different channels. Default for > subsheet is Sn/Sn/Rx there where are two level of hierachy but it > use quite a lot of space. To add an integer value to refdes use > less space. I could add some kind of wild card so that both > changing subsheet and adding an integer value to current subsheet > works? > >>> > >>> I also add comment then this is used. Sometimes layout data > need to be reused for several channels and in such case it is > possible to simply select the layout, copy, rename refdeses and > paste. Then doing a multi channel copy and paste really speed up > design work. > >>> > >> For this purpose, if you have a schematic, I just use "Autonumber > >> attributes" in gschem ... > > Well gschem is not a problem. If you have done the layout of one > channel for example a half bridge in a three phase circuit it is > possiblo to copy and paste this layout including lines for copper > traces but to get connections right refdeses must be changed. > > > > To copy layout for one a channel in pcb is really powerful yet > simple to understand. Ideally somewhere in the future I think > selector to select which subcircuit currently is worked on for > this purpose would be an improvement but simple copy is > essentially already there. > > > > Nicklas Karlsson > I can see your dilemma. Perhaps the best way to handle this (as I've > seen in other apps) is simply to add a '_copy' suffix to the > refdes when > you paste it, and then handle renaming from there. It's a difficult > case, I can see what you'd like to do .. but in practise I think > there's > a lot of code required to figure out your netlisting mix/match .. the > software has no way of knowing where your 'new' circuit has come from, > or what you want to 'assign' it to in an existing > netlist/schematic, so > it would have to be a very simple rename rule. > > MJE > --------------000000050303050703070608 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit Think you've hit the nail on the head really here Peter, and you have better knowledge of the code than I ...

On 19/01/16 15:53, Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] wrote:

Really you need to have a reuse at the schematic level before you can expect any intelligent behaviour in the pcb tool.

I've done multi channel designs with hierarchical schematics before... The rename just becomes X1/R1 -> X2/R1 etc...

My rename plugin might still be floating about somewhere "sedrename"... Now we've got more plugins committed with the main repository, it might be fun to dig that one out and include it too... Was very handy when your transformation between channels can be expressed as a regex.

The main downside with heirarchical refdes is the silkscreen and board fab house. They HATED IT. Couldn't cope with the long heirarchical refdes, didn't WANT to cope with the patch I applied to just put the last heirarchical part on the silk by each part, but then drew boxes manually with module designations.

In the end, I used pcb's renumber feature to assign completely new refdes on the board, but instead of back annotating (impossible as we stand, with heirarchical schematics), I added a quick kludgy patch to read back in the rename file, so pcb could map between the gnetlist produced heirarchical netlist, and the flat refdes on the board.

Made debugging extra fun, having to manually indirect from heirarchical schematic refdes to on board refdes, but at least it didn't upset the board assembly fab!

I suppose I could also have post proceed out a flattened set of schematics with the renamed refdes if that became useful.

Peter

On 19 Jan 2016 14:51, "M. J. Everitt (m DOT j DOT everitt AT iee DOT org) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> wrote:

On 19/01/16 13:58, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via
geda-user AT delorie DOT com] wrote:
>>> I tested and as far as I understand it works like this:
>>> x is old refdes number
>>> n increase with this value
>>> Rx --> Rx+n
>>>
>>> I have subsheets and numbers look like this:
>>> x is old refdes number
>>> n increase with this value
>>> want this S2/S1/Rx --> S2/S1+n/Rx
>>> but get this S2/S1/Rx --> S2/S1+n/Rx
>>> and the need is to change subsheet number and use this for another channel.
>>>
>>> For rename to work reasonable well there must be an integer difference between refdeses for different channels. Default for subsheet is Sn/Sn/Rx there where are two level of hierachy but it use quite a lot of space. To add an integer value to refdes use less space. I could add some kind of wild card so that both changing subsheet and adding an integer value to current subsheet works?
>>>
>>> I also add comment then this is used. Sometimes layout data need to be reused for several channels and in such case it is possible to simply select the layout, copy, rename refdeses and paste. Then doing a multi channel copy and paste really speed up design work.
>>>
>> For this purpose, if you have a schematic, I just use "Autonumber
>> attributes" in gschem ...
> Well gschem is not a problem. If you have done the layout of one channel for example a half bridge in a three phase circuit it is possiblo to copy and paste this layout including lines for copper traces but to get connections right refdeses must be changed.
>
> To copy layout for one a channel in pcb is really powerful yet simple to understand. Ideally somewhere in the future I think selector to select which subcircuit currently is worked on for this purpose would be an improvement but simple copy is essentially already there.
>
> Nicklas Karlsson
I can see your dilemma. Perhaps the best way to handle this (as I've
seen in other apps) is simply to add a '_copy' suffix to the refdes when
you paste it, and then handle renaming from there. It's a difficult
case, I can see what you'd like to do .. but in practise I think there's
a lot of code required to figure out your netlisting mix/match .. the
software has no way of knowing where your 'new' circuit has come from,
or what you want to 'assign' it to in an existing netlist/schematic, so
it would have to be a very simple rename rule.

MJE

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