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Date: Sat, 16 Jan 2016 17:11:01 -0500
Message-Id: <201601162211.u0GMB1E4032505@envy.delorie.com>
From: DJ Delorie <dj AT delorie DOT com>
To: geda-user AT delorie DOT com
In-reply-to: <0E73A3F8-8B1B-4C2A-9792-766AA724905D@noqsi.com> (message from
	John Doty on Sat, 16 Jan 2016 14:18:58 -0700)
Subject: Re: [geda-user] first attempt at bus support in gnetlist for pcb
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> By default, a net nBL,A[8:2] internal to a subcircuit with refdes A1
> will get the name A1/nBL,A[8:2] when gnetlist flattens
> hierarchy. That won't expand right. And note that the user can
> decide to use a different separator and whether hierarchy is prefix
> or postfix in gnetlistrc, so it isn't as simple as looking for the
> last /.

Hmmm... so introducing the <> syntax, either explicitly or as part of
the netlisting, gives us a foo/<a,b,c> -> foo/a,foo/b,foo/c path?

I think my [] syntax could be made nestable, and expanded to include
<> or () pairings.  Perhaps the netlister could auto-wrap everything
in a sub-circuit, then expand everything back up.

In the case where we *don't* flatten, we can still expand busses on
either side of the boundary, but I don't know how that affects the
net-matching mechanism in gnetlist to stitch the heirarchy together.

> > Sigh.
> 
> What do you expect?

Just sighing because it's yet another not-easy-to-do-generically
problem.