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Subject: Re: [geda-user] Primitive electrical types --> layers
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Date: Mon, 11 Jan 2016 11:41:22 +0000
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On 11/01/16 11:25, Stephan Böttcher (geda AT psjt DOT org) [via
geda-user AT delorie DOT com] wrote:
> "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via
> geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:
>
>>>>>   3. For board outline is a good idea to use a filled polygon instead of a line?
>>>>>   4. For a board howto draw a slit? Cutout in outline polygon?
>>>> My board vendors reliably mill my boards by the outline gerber, with
>>>> lines on the outline. 
>>> Same here. A global outline that indicates where there is some material
>>> is useful. Actually my preferred board house wants them drawn with a 1µ
>>> line width, which always makes DRC complain. So one of my feature request 
>>> would be to not run DRC on outline layers, or have per layer DRC rule,
>>> which is a good idea anyway (rules may depend on copper thickness which
>>> can be different on different layers).
>>>
>>>> Did anybody had boards made where the outline was
>>>> specified as a polygon?
>>> Not me.
>>>
>>>     Gabriel
>> A polygon might still make sense and let exporter solve the outline
>> problem. 
> I want the Gerber exporter to export exactly what I draw.  And I will
> draw exactly what the boardhouse wants.  And I don't want the PCB
> program to complain if it assigns semantics in a different way as the
> boardhouse.
>
> If somebody insists on 3D models in a PCB layout tool, then there need
> to be separate drawings for the boardhouse and the 3D model.  And the
> programm please work well without any of the 3D stuff drawn.
>
>> Do you know how they want cut outs drawn?
> No, but I guess they will tell me, and then I will draw that.
>
Well put Stephan.