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Date: Sat, 9 Jan 2016 18:13:45 +0100
From: "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Subject: Re: [geda-user] (features: layers stack, padstack/vias)
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> > One of the things I find confusing about pcb is that layers have types.
> > That’s not physics. Layers are made of materials.
> >
> >
> Whilst I feel you are probably being pedantic on this point, I actually
> agree with you.
> 
> I think you would enjoy reading about the STEP AP210 board stack model.
> (Actually, it is called a layered interconnect model). See this for the
> basic concepts:
> http://www.wikistep.org/index.php/AP210ed2_concept_of_operations
> ...
> All entirely physics and materials based, _including_ explicitly defining

I can see no problem add this http://www.wikistep.org/images/3/37/Stratum.gif to the layer dialog although layer shown on left hand while drawing need to be limited for practical purposes.

For ordinary circuit boards all insulation layers usually have exactly the same drawing primitives. I would say drawing primitives on layer "outline" for the most common circuit boards end up on all insulating layers.

For an embedded component which I only recently heard about their need to be a cut out in the inner insulating layers. If it where possible to put drawing primitive on insulating layer this could be done. It would probably be better to draw a cut out with a certain height and put the cutout at the layers then using the footprint. The footprint could be placed at any layer facing upwards or downwards with only practical limitations, the manufacturer would probably complain for a component facing inwards on outer layer but the limit would not be with the software. This is probably a bit out but if the functionality to draw on any layer is there it should not be to hard to implement although this may not be the case now.

I have started to look at clearance between any net and think about building pin/via/pad from ordinary drawing primitives possible by the old method as a macro for the most common cases. Basically I think about clearance for a line as drawing an enlarged line negative/cutout in polygons for the other nets although other objects have to be saved to the DRC check there instead intersections are calculated.


Nicklas Karlsson