X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com Message-ID: <568FB8A5.4040405@iee.org> Date: Fri, 08 Jan 2016 13:24:53 +0000 From: "M. J. Everitt (m DOT j DOT everitt AT iee DOT org) [via geda-user AT delorie DOT com]" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: geda-user AT delorie DOT com Subject: Re: [geda-user] first attempt at bus support in gnetlist for pcb References: <201601080714 DOT u087Ejj5032766 AT envy DOT delorie DOT com> In-Reply-To: Content-Type: multipart/alternative; boundary="------------030800090304010109090904" X-Provags-ID: V03:K0:iBBHLsdPaXoEAzgrw6AUDyBZUp3ufnq5PgyEJTGvJBE0b3fFjyK gjekbLv7Qbqlfo9ynssE184VcmJ9D/wGXI3VzogG8yOnn2G24AFwcjw1E6cJ4mY8kirOV0T bs4CZLce9zHrRmd0bLACKQ5C8++8KXdoeYxx5ifnW4bsuN9JzWDD9Cat6372HL6pGpWsOvj 4LDzw35z6+SFtVeFFsZhg== X-UI-Out-Filterresults: notjunk:1;V01:K0:FYA9IIKgXns=:sNAoQJ2xxPNAldts6XRbhj hkc9Cu7P77ACoALXdOjkiJyFL96v6eJss8hB1OwxQblqv44p7dtCz+P/jczGJz90n2XKF5i5A hqHGbECqUaNBEUOVI4c77Jo+eWJgYYACctD2mhFd7ZO44QbrOixEEfMAn3o8TWFmLN+Er4y1L MEcDV8K5ODOO5Hl1dznHmAztcH7XKmyXb+VEi5dzDNwG77N4vDcTd+1OH3HiEuCFoWklkqEIg E+Ss2lJkRA96ZOfX8ky9dU8J7gwjvVsa2t7aH+zPJvLicuMYRYSsb6z8/GUlilXxild24w8vc SSQE/pSkTRsgsbUuvAcvXTH+6As3Td/WqVEBgQGg72G/hyo6U7Sqmi5vjNbzDsTfYZPoiujwA XLp3oqOt9uP13JQ297kUL/BSDM691WFoLVSjGSG6oTwfFzR4xXgSHAQk7d3OG0j5dwWttfThK HlrYj9o+F96EdDXu5sWqhbJuAmn+ccVVktFE8bbQhoRuIWjOjDHDTnKmyPH/m+Bok5OPiOzXk kpY75pngqOW4vViegUJwpL2lgUPzOe7g0kDsAZe/wC9ZkkN4EBPb3tlTk0MVQ22BO2McP0DyD qJvaFWnNiUZu4F/25k12pZelZ2LfLHMjGVfwrsi6OdoVUP7MLiXPMAB6COPe2uQ47TSZK44CR sQqYrDODvh3JamRV0TJumxR4Kkwk2Y2oRrDsRdDYu4z1EdvUqROCQ0Rv+oUK4wjYl2gW3Mld0 BFkZoLb08Ls+dGMa Reply-To: geda-user AT delorie DOT com This is a multi-part message in MIME format. --------------030800090304010109090904 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit I propose filing a 'bug' or 'feature request' on one of the central systems, so we can look at getting this completed and tested, if everyone agrees? Can then link it to commits, etc ... merge, release!?! MJE On 08/01/16 12:38, John Doty wrote: > > On Jan 8, 2016, at 6:41 AM, Peter Clifton > (petercjclifton AT googlemail DOT com ) > [via geda-user AT delorie DOT com ] > > wrote: > >> >> On 8 Jan 2016 07:17, "DJ Delorie" > > wrote: >> > >> >> > The net result of this is that you can assign a net named >> "nBL,A[8-2]" to >> > a pin labelled "A[0-7]" and numbered "1-4,10-7" and they'll all get >> > hooked up as appropriate. >> >> Presumably this operates with "normal" nets and pins, not gschem >> buses - which still (as far as I recall) don't netlist. >> >> > You can also have a pin named "GND" and numbered "1,15,18" connected >> > to net "GND" and it will connect all three pins to the one net. >> >> > Constructive feedback welcome! >> >> I think the solution you proposed looks useful and pragmatic. >> >> One potential disadvantage of using this, (user choice of course), is >> that until more work on applying new semantic rules is done in geda, >> schematics using this new attribute semantics will be less easily >> reused for other work like simulation. >> >> > > You can do this kind of thing with a plug-in that wraps the > appropriate gnetlist primitives. It’s somewhat harder, but could apply > to most back ends, not just pcb. >> >> Regarding bus pins & buses vs. Net pins and nets.... I start to >> wonder if we should aim to reduce that distinction in the future, and >> make all nets / pins / buses more equally handled in gEDA. (Up to the >> netlist backend / resolver). >> >> > > Yes. And then, erase the distinction between nets, busses, pins, and > lines. Move that into attributes: a line with netname= is a net, a > line with pinnumber= is a pin … > > This would let the user decide the appropriate line style for nets, > busses, and pins. Keep the old method for backward compatibility, of > course. >> >> Optional stronger port typing like VHDL / verilog would also be nice, >> for schematics that drive hdl output. >> >> > > That kind of thing belongs in a DRC script, I think. >> >> Please can anyone replying consider whether a new thread is >> appropriate if addressing my comments, not DJ's new feature. >> >> > DJ >> > > John Doty Noqsi Aerospace, Ltd. > > http://www.noqsi.com/ > > jpd AT noqsi DOT com > > > --------------030800090304010109090904 Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: 8bit I propose filing a 'bug' or 'feature request' on one of the central systems, so we can look at getting this completed and tested, if everyone agrees? Can then link it to commits, etc ... merge, release!?!

MJE

On 08/01/16 12:38, John Doty wrote:



On 8 Jan 2016 07:17, "DJ Delorie" <dj AT delorie DOT com> wrote:
>

> The net result of this is that you can assign a net named "nBL,A[8-2]" to
> a pin labelled "A[0-7]" and numbered "1-4,10-7" and they'll all get
> hooked up as appropriate.

Presumably this operates with "normal" nets and pins, not gschem buses - which still (as far as I recall) don't netlist.

> You can also have a pin named "GND" and numbered "1,15,18" connected
> to net "GND" and it will connect all three pins to the one net.

> Constructive feedback welcome!

I think the solution you proposed looks useful and pragmatic.

One potential disadvantage of using this, (user choice of course), is that until more work on applying new semantic rules is done in geda, schematics using this new attribute semantics will be less easily reused for other work like simulation.



You can do this kind of thing with a plug-in that wraps the appropriate gnetlist primitives. It’s somewhat harder, but could apply to most back ends, not just pcb.

Regarding bus pins & buses vs. Net pins and nets.... I start to wonder if we should aim to reduce that distinction in the future, and make all nets / pins / buses more equally handled in gEDA. (Up to the netlist backend / resolver).



Yes. And then, erase the distinction between nets, busses, pins, and lines. Move that into attributes: a line with netname= is a net, a line with pinnumber= is a pin …

This would let the user decide the appropriate line style for nets, busses, and pins. Keep the old method for backward compatibility, of course.

Optional stronger port typing like VHDL / verilog would also be nice, for schematics that drive hdl output.



That kind of thing belongs in a DRC script, I think.

Please can anyone replying consider whether a new thread is appropriate if addressing my comments, not DJ's new feature.

> DJ


John Doty              Noqsi Aerospace, Ltd.

http://www.noqsi.com/

jpd AT noqsi DOT com


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