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Date: Fri, 8 Jan 2016 11:41:28 +0000
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Subject: Re: [geda-user] first attempt at bus support in gnetlist for pcb
From: "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 8 Jan 2016 07:17, "DJ Delorie" <dj AT delorie DOT com> wrote:
>

> The net result of this is that you can assign a net named "nBL,A[8-2]" to
> a pin labelled "A[0-7]" and numbered "1-4,10-7" and they'll all get
> hooked up as appropriate.

Presumably this operates with "normal" nets and pins, not gschem buses -
which still (as far as I recall) don't netlist.

> You can also have a pin named "GND" and numbered "1,15,18" connected
> to net "GND" and it will connect all three pins to the one net.

> Constructive feedback welcome!

I think the solution you proposed looks useful and pragmatic.

One potential disadvantage of using this, (user choice of course), is that
until more work on applying new semantic rules is done in geda, schematics
using this new attribute semantics will be less easily reused for other
work like simulation.

Regarding bus pins & buses vs. Net pins and nets.... I start to wonder if
we should aim to reduce that distinction in the future, and make all nets /
pins / buses more equally handled in gEDA. (Up to the netlist backend /
resolver).

Optional stronger port typing like VHDL / verilog would also be nice, for
schematics that drive hdl output.

Please can anyone replying consider whether a new thread is appropriate if
addressing my comments, not DJ's new feature.

> DJ

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<p dir=3D"ltr"><br>
On 8 Jan 2016 07:17, &quot;DJ Delorie&quot; &lt;<a href=3D"mailto:dj AT delori=
e.com">dj AT delorie DOT com</a>&gt; wrote:<br>
&gt;<br></p>
<p dir=3D"ltr">&gt; The net result of this is that you can assign a net nam=
ed &quot;nBL,A[8-2]&quot; to<br>
&gt; a pin labelled &quot;A[0-7]&quot; and numbered &quot;1-4,10-7&quot; an=
d they&#39;ll all get<br>
&gt; hooked up as appropriate.</p>
<p dir=3D"ltr">Presumably this operates with &quot;normal&quot; nets and pi=
ns, not gschem buses - which still (as far as I recall) don&#39;t netlist.<=
/p>
<p dir=3D"ltr">&gt; You can also have a pin named &quot;GND&quot; and numbe=
red &quot;1,15,18&quot; connected<br>
&gt; to net &quot;GND&quot; and it will connect all three pins to the one n=
et.</p>
<p dir=3D"ltr">&gt; Constructive feedback welcome!</p>
<p dir=3D"ltr">I think the solution you proposed looks useful and pragmatic=
.</p>
<p dir=3D"ltr">One potential disadvantage of using this, (user choice of co=
urse), is that until more work on applying new semantic rules is done in ge=
da, schematics using this new attribute semantics will be less easily reuse=
d for other work like simulation.</p>
<p dir=3D"ltr">Regarding bus pins &amp; buses vs. Net pins and nets.... I s=
tart to wonder if we should aim to reduce that distinction in the future, a=
nd make all nets / pins / buses more equally handled in gEDA. (Up to the ne=
tlist backend / resolver).</p>
<p dir=3D"ltr">Optional stronger port typing like VHDL / verilog would also=
 be nice, for schematics that drive hdl output.</p>
<p dir=3D"ltr">Please can anyone replying consider whether a new thread is =
appropriate if addressing my comments, not DJ&#39;s new feature.<br><br></p=
>
<p dir=3D"ltr">&gt; DJ<br>
</p>

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