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Subject: Re: [geda-user] Project leadership (design error in the core of gschem)
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From: John Doty <jpd AT noqsi DOT com>
In-Reply-To: <CAGde_xPez2CmRd7PpsXkf6Oz5g8CbpM=rf39qavgXwBmndVdEA@mail.gmail.com>
Date: Tue, 29 Dec 2015 13:29:03 -0700
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On Dec 29, 2015, at 1:05 PM, Svenn Are Bjerkem =
(svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com] =
<geda-user AT delorie DOT com> wrote:

> On 29 December 2015 at 20:35, John Doty <jpd AT noqsi DOT com> wrote:
>> I just do that with pins2gsch. Draw a small box for the FPGA, with a =
bus running to it. For my most recent project, the connections are =
extracted from the Vivado export, so when the FPGA designer scrambles =
pins on me, it automagically propagates to the netlist.
>=20
> Is that a graphical bus line, and is that bus actually connecting any
> pins with some kind of bus notation, or is it just cosmetic sugar?

The bus is cosmetic sugar, as always. The box is not: it=92s an actual =
symbol with a refdes and footprint for gnetlist to chew on.

>=20
> --
> Svenn
>=20
>=20

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com



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