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Subject: Re: [geda-user] Project leadership (design error in the core of gschem)
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On 29 December 2015 at 20:35, John Doty <jpd AT noqsi DOT com> wrote:
> I just do that with pins2gsch. Draw a small box for the FPGA, with a bus running to it. For my most recent project, the connections are extracted from the Vivado export, so when the FPGA designer scrambles pins on me, it automagically propagates to the netlist.

Is that a graphical bus line, and is that bus actually connecting any
pins with some kind of bus notation, or is it just cosmetic sugar?

-- 
Svenn