On Wed, Dec 23, 2015 at 12:28 AM, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-use= r AT delorie DOT com> wrote:

> = On Tue, Dec 22, 2015 at 1:02 PM, Peter Clifton (
> petercjclifton AT google= mail.com) [via geda-user AT delor= ie.com] <
> geda-user AT delorie DOT com>= wrote:
>
> > > Then there is the problem is there is an unconnected object = within
> > distance but I guess it could worked around if not already done b= y at least
> > temporary assign all objects to a net.
> >
> > I "think" this works ok, but I'm on a Win7 box with= no PCB right now
> > to check... OK, no wait - I did install PCB (remember it also por= ts to
> > Win32 if you like masochism)...
> >
> >
> > So - it "nearly" works.. two tracks violating DRC clear= ance, on a
> > board with no netlist - no DRC results.
> > Throw down a via, and touch it to one of those tracks - and we se= e 1x
> > DRC violations - "Copper areas too close".
> >
> > Bug - one I'm sure could be fixed. We're probably just no= t iterating
> > over all of the non "PV" type objects as potential DRC = check
> > start-points. (DRC draws a distinction between the in-layer objec= ts
> > like lines, arcs, polygons etc.. and the "PV" type obje= cts (pin, via),
> > which can traverse layers..
> >
>
> Yes this would be fairly straightforward to fix.=C2=A0 Variable cleara= nce values
> would be fairly easy to do as well, at least in an inefficient way:=C2= =A0 find.c
> uses a single global "bloat" value to check for connection c= hanges at given
> bloats (which can be negative).=C2=A0 To handle a board with variable = clearance
> requirements, you could just start with the lowest clearance and re-ru= n the
> entire board for each different clearance value.=C2=A0 If there weren&= #39;t too
> terribly many it wouldn't be too slow.=C2=A0 Traces with larger cl= earance
> requirements probably also deserve larger overlap requirements, so you= 'd
> probably actually need two additional passes for each "special&qu= ot; wire class.
>
> Britton

different net<-->net clearances should not be to hard once every obje= ct on copper layer have been assigned a net name:
=C2=A0 1. Check global value as is done now.
=C2=A0 2. Check clerance for each other net<-->net combintion, during= this pass all other nets could be ignored.
The trick is for each net with a particular value you check clearance to th= e other nets instead of all nets at once.

I think = you can accomplish this with a run of the existing code along only the high= -clearance wires, and an elevated bloat setting.=C2=A0 Then you would be us= ing all the same code, admittedly in a slightly tortured way.=C2=A0