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Date: Tue, 22 Dec 2015 21:43:28 +0000
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Subject: Re: [geda-user] Project leadership
From: "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Precedence: bulk

I think your suggested flow captures it...

I'm presuming ueda has an element which can parse the verilog into a
PCB netlist.


Longer term, I'd love to see the "core" ("EdaCore" or "openEDA" -
whatever) library support the primitive concept of netlists, and we
could just teach _that_ to read verilog, as well as the gschem stuff
(then merge from multiple sources into one netlist - and spit out via
whatever backend / plugin suits your target environment).

Bonus points for PCB using the core-library too, so it can "give up"
its one preferred on-disk netlist format, and read any useful ones we
care to implement a reader for in the core EDA library.

Peter

On 22 December 2015 at 21:33, Stephan Böttcher <geda AT psjt DOT org> wrote:
>
> "Peter Clifton (petercjclifton AT googlemail DOT com) [via
> geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:
>
>> I really believe you are on to a very strong concept here...
>> schematics have their place IMO, but look at many modern designs
>> (laptop etc., say?) and see how that graphical the format of
>> schematics is really being pushed beyond its most effective.
>
> People tell me that a schematic drawing should illustrate the function
> of a circuit.  But most of that function is hidden inside the µC and
> FPGA.  So, my symbols and schematics are more a preview of the layout,
> to get a good first shot at (functionally arbitrary) pin assignements.
>
> Like this one:  http://www.ieap.uni-kiel.de/et/people/stephan/rpirena/
>
> I thought about using Verilog as netlist format for PCBs.  How would I
> convert those to pcb netlists, with some graphical drawings added in the
> mix?
>
>  gschem, gnetlist --> Verilog
>  Verilog --> ueda --> PCB netlist
>
> ?
>
> --
> Stephan
>