X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com X-Envelope-From: paubert AT iram DOT es Date: Sun, 13 Sep 2015 00:21:03 +0200 From: "Gabriel Paubert (paubert AT iram DOT es) [via geda-user AT delorie DOT com]" To: "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" Subject: Re: [geda-user] zero soldermask clearance not caught by DRC Message-ID: <20150912222103.GA24082@visitor2.iram.es> References: <55F1640D DOT 5080703 AT envinsci DOT co DOT uk> <6a568918 DOT 155e DOT 14fbbfe5daa DOT Webtop DOT 41 AT optonline DOT net> <20150911132906 DOT d98b30cc9a57a7d037b8fb3a AT gmail DOT com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150911132906.d98b30cc9a57a7d037b8fb3a@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Spamina-Bogosity: Unsure X-Spamina-Spam-Score: -1.0 (-) X-Spamina-Spam-Report: Content analysis details: (-1.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: latticesemi.com] -0.0 BAYES_20 BODY: Bayes spam probability is 5 to 20% [score: 0.0906] Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Fri, Sep 11, 2015 at 01:29:06PM +0200, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] wrote: > On Fri, 11 Sep 2015 06:40:53 -0400 (EDT) > GENE GLICK wrote: > > > I don't think you are going to have any problems. I've worked with > > layout guys who routinely have 0 clearance on the soldermask. The board > > fab houses will adjust their process, sometimes without telling you. At > > work, we use a pretty good place, and they will adjust the clearance up > > or down as needed. I think the fab houses have to make adjustments to > > your design in order to work with the tolerances of their own processes. > > > > Anyway, you can ask the fab house if they fix that sort of stuff up or > > not. > > Usually solder mask is a little bit larger to not cover any of the pad. I guess you will be able to solder the part even if "visible" pad is a little bit smaller because of tolerance problem with solder mask. While this is the general rule, guidelines for small pitch BGA (0.5 mm and lower) often recommend using SMD (solder mask defined) pads: http://latticesemi.com/view_document?document_id=671 Gabriel