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Date: Sat, 12 Sep 2015 17:29:16 GMT
From: falcon AT ivan DOT Harhan DOT ORG (Spacefalcon the Outlaw)
Message-Id: <1509121729.AA26401@ivan.Harhan.ORG>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] About reinventing the wheel, and how to avoid it
Reply-To: geda-user AT delorie DOT com

Evan Foss (evanfoss AT gmail DOT com) wrote:

> The flows to and from pcb are not as
> diverse there is really only one schematic capture program that can
> flow into it.

Wrong, there is an alternative way to feed design netlists to PCB that
does not involve gschem or any other graphical schematics.  I gave up
on graphical schematics as drawing them is too much extra work which I
am not good at and which I would rather skip, and now I do my board
designs using the structural subset of Verilog as my design entry
language, i.e., text-based instead of graphics.

My flow is best illustrated by the example of the design I'm currently
working on.  Here is a historical graphical schematic drawing (OrCAD)
for the design I am re-creating:

ftp://ftp.freecalypso.org/pub/GSM/Calypso/Leonardo_rev05.pdf

And here is my re-creation of that board in my own design environment:

https://bitbucket.org/falconian/freecalypso-schem

And here is the C source for my Makefile-driven tools that compile the
design source (structural Verilog, Master Component List, BGA package
and pinout definitions and other bits of input) into a netlist for PCB
import (either GNU PCB or PADS):

https://bitbucket.org/falconian/ueda-linux

> Solving the back annotation issue (which is seeing some
> serious progress) will I hope resolve this.

There is no place for back annotation in a flow like mine.  I don't
want my source code to be edited by anyone other than me.

In my flow, if a need for a pin or slot swap or somesuch is discovered
during layout, one makes the appropriate trivial change to the
appropriate source file and reruns 'make'.

SF