X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
Date: Wed, 9 Sep 2015 14:09:05 -0400
Message-Id: <201509091809.t89I95SI022282@envy.delorie.com>
From: DJ Delorie <dj AT delorie DOT com>
To: geda-user AT delorie DOT com
In-reply-to: <EA4D92E5-7674-49D8-911E-1318E2F1CEF1@sbcglobal.net>
	(geda-user AT delorie DOT com)
Subject: Re: [geda-user] New experimental netlist features
References: <alpine DOT DEB DOT 2 DOT 11 DOT 1509031356150 DOT 13201 AT nimbus> <msi77b$6rr$1 AT ger DOT gmane DOT org> <alpine DOT DEB DOT 2 DOT 00 DOT 1509082036590 DOT 3066 AT lichen> <201509082040 DOT t88KerD6005455 AT envy DOT delorie DOT com> <EA4D92E5-7674-49D8-911E-1318E2F1CEF1 AT sbcglobal DOT net>
Reply-To: geda-user AT delorie DOT com
Errors-To: nobody AT delorie DOT com
X-Mailing-List: geda-user AT delorie DOT com
X-Unsubscribes-To: listserv AT delorie DOT com
Precedence: bulk


> Would this proposed feature also work for connecting a single pin to
> multiple pads? For example, could three pin symbols for transistors
> work with devices that have four pads? It would be nice to support
> all the relationships:

In my blue-sky world, this problem is handled by the pin-mapping idea:

http://www.delorie.com/pcb/pin-mapping.html

Combining the two, you'd have gschem see this:

  netname="CS7,nWR,D[15:8]"
  pinlabel="nCS,nWRITE,Data[7:0]"

And the selection of a component would provide a pin mapping:

  nCS = 1
  nWRITE = 2
  (D7,D6,D5,D4,D3,D2,D1,D0) = (3,4,5,6,7,8,9,10)
      (maybe it's a ram chip and the order of data pins doesn't matter)

For transistors you might end up with a mapping like:

  G = 1
  S = 2
  D = 3,4