On Tue, Sep 8, 2015 at 5:58 PM, DJ Delorie <dj AT delorie DOT com>= wrote:

> If a buss is labelled

buss (n) a kiss, or (v) to kiss.=C2=A0 I don't label mine ;-)
> [0..3] and is in contact with a buss having label x[0..31] all the
> info is there to figure out that the [0..3] buss is called x[0..3]

It's the "and is in contact with" that's the probl= em.=C2=A0 In gnetlist,
all net segments that are connected are considered as one net.=C2=A0 A
collection of connected bus segments would be one bus.=C2=A0 Naming
different segments of that bus differently causes ambiguity.

The problem is as pictured here:

=C2=A0 http://www.delorie.com/pcb/bus-pins.html

If a bus has multiple signals in it, and you give different ends (or
branches) of the bus different netnames, you've created a conflict
that the netlister has to magically resolve.

The way bus segments work *now*, the bus segment itself is the magic
that keeps the nets connected to the bus rippers from being
"connected" and thus they're allowed to have different names.=

I for one usually think of a b= us as several different signals that are always used together such as a mic= roprocessor

bus with have address, data and control signals.<= br>

I would use vector for what you are calling a bus if it i= s only one signal name and a width.

The problem with = PCB netlists is that digital design always uses a subset of verilog known a= s "synthesisable verilog" for

all design work. Only= the testbench can use the entire language.

PCB design i= s actually a superset of verilog. You can run a piece of metal between any = two nodes and have a valid circuit

that will be a real mess = for the netlister to understand. I can have a 34 pin flat cable connector w= ith 17 signals on the odd

pins and ground on all the evens. = Feed that to verilog and it will puke. A component can have multiple pins w= ith the same

name and those pins are all shorted together. So= lder it to a board and you change the netlist.

A verilog = netlister has to do more than simply converting syntax. Sometimes it has to= resolve aliases and put in transmission

gates.

I am also not thrilled with the current bus rippers. The two compo= nent rippers only have one hot spot so the connection is made by name
<= /div>

only, it works even if its not on the correct bus. The third opti= on of using a net as a bus ripper does have two hot spots and works

correctly. Adding a second hot spot to the rippers should fix that.<= br>

John Eaton

<= br>

=C2=A0

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