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DJ wrote:
>
> In verilog, isn't the :N syntax used to denote the signal's *width* ?
> I.e. 0:8 would be the lower byte, 8:8 would be the upper byte, etc.
> If so, using the same syntax for a different meaning might confuse
> people.

I don't know about Verilog, but VHDL has 
std_logic_vector(7 downto 0); and std_logic_vector(0 to 7);

which are 8-bit. I wonder if there is possibility to use idea of
indexing begins from zero and ends before length. 

Hannu Vuolasaho