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Subject: Re: [geda-user] Anybody using gschem for VHDL structural design?
From: "Svenn Are Bjerkem (svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 8 September 2015 at 12:31, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com)
[via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

> I am not using it but it seems like a really good idea!
>

It is a good idea. But there is a lot of stuff to do to get where I want.
Robert has a good introduction to the topic. Short and on the spot for
starters.

I do FPGA design, mostly in vim. It is tedious to maintain a good bird view
unless a separate block diagram is continously updated for the purpose of
communication with colleagues.

The challenge is that while PCB design with gschem is pretty static
regarding the pinout of devices, an FPGA design may be very dynamic
internally regarding ports on entities, at least in the initial phase of a
design: Add an instance and suddenly the parent entity has loads of extra
ports.

To have symbol-from-schematic and symbol-update-from-schematic would be
very handy (this is also valid for ASIC, so I wonder if somebod already has
the feature developed)

symbol-from-entity is also something I look at. Currently I punch my pins
in DJ's symbol generator.

VHDL generics seems to be missing for the time being. Need to go through
some scheme unless the xorn  backend is better.

-- 
Svenn

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<div dir=3D"ltr"><div><div><div><div class=3D"gmail_extra"><div class=3D"gm=
ail_quote">On 8 September 2015 at 12:31, Nicklas Karlsson (<a href=3D"mailt=
o:nicklas DOT karlsson17 AT gmail DOT com">nicklas DOT karlsson17 AT gmail DOT com</a>) [via <a h=
ref=3D"mailto:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>] <span dir=
=3D"ltr">&lt;<a href=3D"mailto:geda-user AT delorie DOT com" target=3D"_blank">ged=
a-user AT delorie DOT com</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quot=
e" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">=
I am not using it but it seems like a really good idea!<br>
</blockquote></div></div><br></div>It is a good idea. But there is a lot of=
 stuff to do to get where I want.<br></div><div>Robert has a good introduct=
ion to the topic. Short and on the spot for starters.<br><br></div><div>I d=
o FPGA design, mostly in vim. It is tedious to maintain a good bird view un=
less a separate block diagram is continously updated for the purpose of com=
munication with colleagues.<br><br></div><div>The challenge is that while P=
CB design with gschem is pretty static regarding the pinout of devices, an =
FPGA design may be very dynamic internally regarding ports on entities, at =
least in the initial phase of a design: Add an instance and suddenly the pa=
rent entity has loads of extra ports.<br><br></div><div>To have symbol-from=
-schematic and symbol-update-from-schematic would be very handy (this is al=
so valid for ASIC, so I wonder if somebod already has the feature developed=
)<br><br></div><div>symbol-from-entity is also something I look at. Current=
ly I punch my pins in DJ&#39;s symbol generator.<br><br></div><div>VHDL gen=
erics seems to be missing for the time being. Need to go through some schem=
e unless the xorn=C2=A0 backend is better.<br></div></div><div><div><div><b=
r>-- <br><div class=3D"gmail_signature">Svenn</div></div></div></div></div>

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