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Subject: Re: developer excitement? was Re: [geda-user] gEDA/gschem still alive?
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One thing that we could do to recruit more developers is to expand geda and
use it in more tools. gschem is nice general purpose drawing tool with
extensions that allow it to do schematic capture for PCB layout, Spice and
verilog simulations.

We could expand gschem to use it as the base for FPGA and ASIC tools. For
example:

Finite State Machine Designer:  Create a data structure for a STATE that is
similar to a component and a TRANSITION that is similar to a wire. You can
then entire a state machine diagram and let it create the verilog.

Timing Diagram Designer: Add some macros and short cuts to make it easier
to create timing diagrams. Read and write verilog VCD files

Design Navigator: read in a verilog hierarchy and automatically  create all
of the geda symbols and schematics.

Busses: gschem currenly only fully supports wires and vectors are only a
graphic. Add full support for vectors and also support busses. Busses are a
budirectional collection of wires and vectors with connections of MASTER or
SLAVE.



If you could extract all of the gschem schematic code and move it into a
separate module then any tool needing a graphics engine would only have to
figure out how to rewire that module for their onw usage.


John Eaton

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<div dir=3D"ltr"><div><div><div><div><div><div><div>One thing that we could=
 do to recruit more developers is to expand geda and use it in more tools. =
gschem is nice general purpose drawing tool with extensions that allow it t=
o do schematic capture for PCB layout, Spice and verilog simulations. <br><=
br></div>We could expand gschem to use it as the base for FPGA and ASIC too=
ls. For example:<br><br></div>Finite State Machine Designer:=C2=A0 Create a=
 data structure for a STATE that is similar to a component and a TRANSITION=
 that is similar to a wire. You can then entire a state machine diagram and=
 let it create the verilog.<br><br></div>Timing Diagram Designer: Add some =
macros and short cuts to make it easier to create timing diagrams. Read and=
 write verilog VCD files<br><br></div>Design Navigator: read in a verilog h=
ierarchy and automatically=C2=A0 create all of the geda symbols and schemat=
ics.<br><br></div>Busses: gschem currenly only fully supports wires and vec=
tors are only a graphic. Add full support for vectors and also support buss=
es. Busses are a budirectional collection of wires and vectors with connect=
ions of MASTER or SLAVE.<br><br><br><br></div>If you could extract all of t=
he gschem schematic code and move it into a separate module then any tool n=
eeding a graphics engine would only have to figure out how to rewire that m=
odule for their onw usage.<br><br><br></div>John Eaton<br><br><br><div><br>=
<div><br>=C2=A0<br><div><div><div><div><br><div><div><div><div><div class=
=3D"gmail_extra"><br></div></div></div></div></div></div></div></div></div>=
</div></div></div>

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