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Date: Thu, 9 Jul 2015 17:57:48 -0400
Message-Id: <201507092157.t69LvmES002837@envy.delorie.com>
From: DJ Delorie <dj AT delorie DOT com>
To: geda-user AT delorie DOT com
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Subject: Re: [geda-user] What is the hardest part in a PCB layout program?
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> The hardest part for me to understand when I look at the code is
> where the geometry is processed vs where it is rendered.

This one is easy.  Rendering is always done in the HID, like
src/hid/gtk or src/hid/ps.  Everything in the core deals with the raw
data or its geometry directly.

> OT: Is DRC checking done via the rendering engine or is there a
> separate geometry engine that does this and verifies when traces and
> etc are connected?

There's a geometry engine in DRC although how it works is totally
counter-intuitive:

* Generate a netlist based on connectivity. (also used by the rats
  list stuff, find, select-nets, etc)

* Now, increase the size of everything by N and generate a new netlist.

* Are the netlists different?  Bug!