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Date: Thu, 9 Jul 2015 09:16:32 -0800
Message-ID: <CAC4O8c8m6moOmgFywHSg77AtHUfpv6VA89Hd4DH3F2XnfXV+NA@mail.gmail.com>
Subject: Re: [geda-user] Back annotation
From: "Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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> For my ASIC designs, the parameter extracted netlists are about 200x the size of the netlists generated from the schematics. Printed circuit designs are generally flatter, but back-annotation into even a simple circuit still looks impractical to me. There’s really no utility to it anyway: the netlist is what you need as input for your verification process.

Since you don't do layout work, how would you know?

Britton