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Subject: Re: [geda-user] Back annotation
From: John Doty <jpd AT noqsi DOT com>
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Date: Thu, 9 Jul 2015 10:48:25 -0600
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On Jul 9, 2015, at 8:35 AM, John Griessen <john AT ecosensory DOT com> wrote:

> Another for instance:  First, run a program that uses geometry and an attrib on a footprint pin to
> search for capacitor components in a radius from the pin that are also attached by conductor, and gather
> up their frequency bands of good functioning attribs in a list.  Then run an import function in gschem
> to update the schematic with those corresponding attrib lists.   The corresponding attrib is not on the capacitor,
> but on the pin, and once you have the pin updated with lists, you run a DRC to tell if enough bypassing is done
> properly, and maybe where there is excess, but probably leave the analyzing of excess to human eyes.

I’ve used this kind of facility in ASIC design, but back-annotation into the schematic is very impractical.

1. A “parameter extracted” netlist is flat. The tool that does the extraction operates on the flat layout. Even if the subcircuits use identical cells, they have different neighbors, so it really must be flat.

2. The parasitics have a complicated topology of their own, different from the network segment topology of a readable schematic.

For my ASIC designs, the parameter extracted netlists are about 200x the size of the netlists generated from the schematics. Printed circuit designs are generally flatter, but back-annotation into even a simple circuit still looks impractical to me. There’s really no utility to it anyway: the netlist is what you need as input for your verification process.



John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com