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Date: Wed, 10 Jun 2015 02:40:29 +0530
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Subject: Re: [geda-user] Problem with BGA footprint generator
From: "Shashank Chintalagiri (shashank DOT chintalagiri AT gmail DOT com)" <geda-user AT delorie DOT com>
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I can't really contribute much to the discussion on what the BGA
standards are. This is the first time I'm going to try to use BGA, and
right now figuring out how to breakout all the traces and subsequently
how they can be installed by hand are more pressing issues for me.

However, the link I originally posted produces footprints inconsistent
with the diagram on the same page. Admittedly, there is a small sense
of ambiguity on whether the diagram is from the top or the bottom, but
personally I don't think a land pattern diagram with silk, etc. can
reasonably be expected to be mirrored (view from bottom) in such a
representation. As such, as far as I'm concerned the generator makes
bad footprints.

On a side note, I've found that the following features would be useful
to have to help with BGA routing:
     - The inherent requirement for close packed vias and lines would
be helped if the vias had different annular ring sizes for internal
layers.
     - DRC and spacing rules (I typically rely primarily on "Crosshair
shows DRC clearance") per layer, or atleast outer and inner layers,
would be nice to have.
     - With a 0.75mm pitch, actually getting a trace to come down
precisely between two pads is impossible on the grid options
available, unless you set a grid size so small that it effectively is
a no-grid type of situation. Having arbitrary grid spacing available
would be nice.



On Wed, Jun 10, 2015 at 2:17 AM, Jonatan Åkerlind <jonatan AT akerlind DOT nu> wrote:
> Do you have examples of that inconsistency? Just checked with the JEDEC
> standard (see below) and also checked a datasheet from Xilinx and LT
> each, and they all agree. I checked these:
>
> www.jedec.org/sites/default/files/docs/SPP-020A.pdf
>
> http://www.linear.com/docs/46540
>
> www.xilinx.com/support/documentation/package_specs/ft256.pdf
>
>
> There seems to have been some ambiguity with the JEDEC standard (JEP95
> SPP-010) regarding this numbering, which was clarified in JEP95
> SPP-020A.
>
> The standard (SPP-020A) states that when viewing the package from top in
> the as-mounted orientation with A1 at the top left corner (i.e. same as
> looking at an unpopulated PCB footprint) the columns are enumerated
> 1,2,3 left-to-right and the rows are enumerated A,B,C top-to-bottom.
>
> But to cite the background from SPP-020A:
> "The numbering practice for grid array packages has been clearly defined
> for square packages in JEP95,
> Section 3, SPP-010. The application of this practice to rectangular
> array packages is ambiguous and has led to inconsistency in the
> numbering shown in JEDEC outlines."
>
> /Jonatan
>
> On tis, 2015-06-09 at 13:21 -0700, Edward Hennessy
> (ehennes AT sbcglobal DOT net) wrote:
>> After looking around, I've found two different pin numbering schemes. (Could be more.)
>>
>> When rotating the package so pin A1 is in the upper left, one scheme uses letters for the rows and numbers for the columns. The other uses numbers for the rows and letters for the columns.
>>
>> Examining datasheets, Linear uses one scheme, and Xilinx uses another.
>>
>> I need to update my footprint generator.
>>
>> Cheers,
>> Ed
>>
>> Sent from my iPhone
>>
>> > On Jun 9, 2015, at 9:11 AM, DJ Delorie <dj AT delorie DOT com> wrote:
>> >
>> >
>> > I wonder if BGAs have the transistor problem... that the tool is
>> > correct for some BGAs and wrong for others, and if we fix it it will
>> > be correct for some BGAs and wrong for others.
>>
>
> --
> Jonatan Åkerlind
> +46702002897
>
>



-- 

Chintalagiri Shashank
Indian Institute of Technology, Kanpur

http://blog.chintal.in